cpu_arm64.go

     1  // Copyright 2017 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  package cpu
     6  
     7  // CacheLinePadSize is used to prevent false sharing of cache lines.
     8  // We choose 128 because Apple Silicon, a.k.a. M1, has 128-byte cache line size.
     9  // It doesn't cost much and is much more future-proof.
    10  const CacheLinePadSize = 128
    11  
    12  func doinit() {
    13  	options = []option{
    14  		{Name: "aes", Feature: &ARM64.HasAES},
    15  		{Name: "pmull", Feature: &ARM64.HasPMULL},
    16  		{Name: "sha1", Feature: &ARM64.HasSHA1},
    17  		{Name: "sha2", Feature: &ARM64.HasSHA2},
    18  		{Name: "sha512", Feature: &ARM64.HasSHA512},
    19  		{Name: "sha3", Feature: &ARM64.HasSHA3},
    20  		{Name: "crc32", Feature: &ARM64.HasCRC32},
    21  		{Name: "atomics", Feature: &ARM64.HasATOMICS},
    22  		{Name: "cpuid", Feature: &ARM64.HasCPUID},
    23  		{Name: "isNeoverse", Feature: &ARM64.IsNeoverse},
    24  	}
    25  
    26  	// arm64 uses different ways to detect CPU features at runtime depending on the operating system.
    27  	osInit()
    28  }
    29  
    30  func getisar0() uint64
    31  
    32  func getisar1() uint64
    33  
    34  func getpfr0() uint64
    35  
    36  func getMIDR() uint64
    37  
    38  func extractBits(data uint64, start, end uint) uint {
    39  	return (uint)(data>>start) & ((1 << (end - start + 1)) - 1)
    40  }
    41  
    42  func parseARM64SystemRegisters(isar0, isa1, pfr0 uint64) {
    43  	// ID_AA64ISAR0_EL1
    44  	// https://developer.arm.com/documentation/ddi0601/2025-03/AArch64-Registers/ID-AA64ISAR0-EL1--AArch64-Instruction-Set-Attribute-Register-0
    45  	switch extractBits(isar0, 4, 7) {
    46  	case 1:
    47  		ARM64.HasAES = true
    48  	case 2:
    49  		ARM64.HasAES = true
    50  		ARM64.HasPMULL = true
    51  	}
    52  
    53  	switch extractBits(isar0, 8, 11) {
    54  	case 1:
    55  		ARM64.HasSHA1 = true
    56  	}
    57  
    58  	switch extractBits(isar0, 12, 15) {
    59  	case 1:
    60  		ARM64.HasSHA2 = true
    61  	case 2:
    62  		ARM64.HasSHA2 = true
    63  		ARM64.HasSHA512 = true
    64  	}
    65  
    66  	switch extractBits(isar0, 16, 19) {
    67  	case 1:
    68  		ARM64.HasCRC32 = true
    69  	}
    70  
    71  	switch extractBits(isar0, 20, 23) {
    72  	case 2:
    73  		ARM64.HasATOMICS = true
    74  	}
    75  
    76  	switch extractBits(isar0, 32, 35) {
    77  	case 1:
    78  		ARM64.HasSHA3 = true
    79  	}
    80  
    81  	switch extractBits(isa1, 36, 39) {
    82  	case 1:
    83  		ARM64.HasSB = true
    84  	}
    85  
    86  	switch extractBits(pfr0, 48, 51) {
    87  	case 1:
    88  		ARM64.HasDIT = true
    89  	}
    90  }
    91
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