Source file src/cmd/internal/obj/riscv/cpu.go

     1  //	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
     2  //	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     3  //	Portions Copyright © 1997-1999 Vita Nuova Limited
     4  //	Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
     5  //	Portions Copyright © 2004,2006 Bruce Ellis
     6  //	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
     7  //	Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
     8  //	Portions Copyright © 2009 The Go Authors.  All rights reserved.
     9  //	Portions Copyright © 2019 The Go Authors.  All rights reserved.
    10  //
    11  // Permission is hereby granted, free of charge, to any person obtaining a copy
    12  // of this software and associated documentation files (the "Software"), to deal
    13  // in the Software without restriction, including without limitation the rights
    14  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    15  // copies of the Software, and to permit persons to whom the Software is
    16  // furnished to do so, subject to the following conditions:
    17  //
    18  // The above copyright notice and this permission notice shall be included in
    19  // all copies or substantial portions of the Software.
    20  //
    21  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    22  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    23  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    24  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    25  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    26  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    27  // THE SOFTWARE.
    28  
    29  package riscv
    30  
    31  import (
    32  	"errors"
    33  	"fmt"
    34  
    35  	"cmd/internal/obj"
    36  )
    37  
    38  var CSRs map[uint16]string = csrs
    39  
    40  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p riscv
    41  
    42  const (
    43  	// Base register numberings.
    44  	REG_X0 = obj.RBaseRISCV + iota
    45  	REG_X1
    46  	REG_X2
    47  	REG_X3
    48  	REG_X4
    49  	REG_X5
    50  	REG_X6
    51  	REG_X7
    52  	REG_X8
    53  	REG_X9
    54  	REG_X10
    55  	REG_X11
    56  	REG_X12
    57  	REG_X13
    58  	REG_X14
    59  	REG_X15
    60  	REG_X16
    61  	REG_X17
    62  	REG_X18
    63  	REG_X19
    64  	REG_X20
    65  	REG_X21
    66  	REG_X22
    67  	REG_X23
    68  	REG_X24
    69  	REG_X25
    70  	REG_X26
    71  	REG_X27
    72  	REG_X28
    73  	REG_X29
    74  	REG_X30
    75  	REG_X31
    76  
    77  	// Floating Point register numberings.
    78  	REG_F0
    79  	REG_F1
    80  	REG_F2
    81  	REG_F3
    82  	REG_F4
    83  	REG_F5
    84  	REG_F6
    85  	REG_F7
    86  	REG_F8
    87  	REG_F9
    88  	REG_F10
    89  	REG_F11
    90  	REG_F12
    91  	REG_F13
    92  	REG_F14
    93  	REG_F15
    94  	REG_F16
    95  	REG_F17
    96  	REG_F18
    97  	REG_F19
    98  	REG_F20
    99  	REG_F21
   100  	REG_F22
   101  	REG_F23
   102  	REG_F24
   103  	REG_F25
   104  	REG_F26
   105  	REG_F27
   106  	REG_F28
   107  	REG_F29
   108  	REG_F30
   109  	REG_F31
   110  
   111  	// Vector register numberings.
   112  	REG_V0
   113  	REG_V1
   114  	REG_V2
   115  	REG_V3
   116  	REG_V4
   117  	REG_V5
   118  	REG_V6
   119  	REG_V7
   120  	REG_V8
   121  	REG_V9
   122  	REG_V10
   123  	REG_V11
   124  	REG_V12
   125  	REG_V13
   126  	REG_V14
   127  	REG_V15
   128  	REG_V16
   129  	REG_V17
   130  	REG_V18
   131  	REG_V19
   132  	REG_V20
   133  	REG_V21
   134  	REG_V22
   135  	REG_V23
   136  	REG_V24
   137  	REG_V25
   138  	REG_V26
   139  	REG_V27
   140  	REG_V28
   141  	REG_V29
   142  	REG_V30
   143  	REG_V31
   144  
   145  	// This marks the end of the register numbering.
   146  	REG_END
   147  
   148  	// General registers reassigned to ABI names.
   149  	REG_ZERO = REG_X0
   150  	REG_RA   = REG_X1 // aka REG_LR
   151  	REG_SP   = REG_X2
   152  	REG_GP   = REG_X3 // aka REG_SB
   153  	REG_TP   = REG_X4
   154  	REG_T0   = REG_X5
   155  	REG_T1   = REG_X6
   156  	REG_T2   = REG_X7
   157  	REG_S0   = REG_X8
   158  	REG_S1   = REG_X9
   159  	REG_A0   = REG_X10
   160  	REG_A1   = REG_X11
   161  	REG_A2   = REG_X12
   162  	REG_A3   = REG_X13
   163  	REG_A4   = REG_X14
   164  	REG_A5   = REG_X15
   165  	REG_A6   = REG_X16
   166  	REG_A7   = REG_X17
   167  	REG_S2   = REG_X18
   168  	REG_S3   = REG_X19
   169  	REG_S4   = REG_X20
   170  	REG_S5   = REG_X21
   171  	REG_S6   = REG_X22
   172  	REG_S7   = REG_X23
   173  	REG_S8   = REG_X24
   174  	REG_S9   = REG_X25
   175  	REG_S10  = REG_X26 // aka REG_CTXT
   176  	REG_S11  = REG_X27 // aka REG_G
   177  	REG_T3   = REG_X28
   178  	REG_T4   = REG_X29
   179  	REG_T5   = REG_X30
   180  	REG_T6   = REG_X31 // aka REG_TMP
   181  
   182  	// Go runtime register names.
   183  	REG_CTXT = REG_S10 // Context for closures.
   184  	REG_G    = REG_S11 // G pointer.
   185  	REG_LR   = REG_RA  // Link register.
   186  	REG_TMP  = REG_T6  // Reserved for assembler use.
   187  
   188  	// ABI names for floating point registers.
   189  	REG_FT0  = REG_F0
   190  	REG_FT1  = REG_F1
   191  	REG_FT2  = REG_F2
   192  	REG_FT3  = REG_F3
   193  	REG_FT4  = REG_F4
   194  	REG_FT5  = REG_F5
   195  	REG_FT6  = REG_F6
   196  	REG_FT7  = REG_F7
   197  	REG_FS0  = REG_F8
   198  	REG_FS1  = REG_F9
   199  	REG_FA0  = REG_F10
   200  	REG_FA1  = REG_F11
   201  	REG_FA2  = REG_F12
   202  	REG_FA3  = REG_F13
   203  	REG_FA4  = REG_F14
   204  	REG_FA5  = REG_F15
   205  	REG_FA6  = REG_F16
   206  	REG_FA7  = REG_F17
   207  	REG_FS2  = REG_F18
   208  	REG_FS3  = REG_F19
   209  	REG_FS4  = REG_F20
   210  	REG_FS5  = REG_F21
   211  	REG_FS6  = REG_F22
   212  	REG_FS7  = REG_F23
   213  	REG_FS8  = REG_F24
   214  	REG_FS9  = REG_F25
   215  	REG_FS10 = REG_F26
   216  	REG_FS11 = REG_F27
   217  	REG_FT8  = REG_F28
   218  	REG_FT9  = REG_F29
   219  	REG_FT10 = REG_F30
   220  	REG_FT11 = REG_F31
   221  
   222  	// Names generated by the SSA compiler.
   223  	REGSP = REG_SP
   224  	REGG  = REG_G
   225  )
   226  
   227  // https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc#dwarf-register-numbers
   228  var RISCV64DWARFRegisters = map[int16]int16{
   229  	// Integer Registers.
   230  	REG_X0:  0,
   231  	REG_X1:  1,
   232  	REG_X2:  2,
   233  	REG_X3:  3,
   234  	REG_X4:  4,
   235  	REG_X5:  5,
   236  	REG_X6:  6,
   237  	REG_X7:  7,
   238  	REG_X8:  8,
   239  	REG_X9:  9,
   240  	REG_X10: 10,
   241  	REG_X11: 11,
   242  	REG_X12: 12,
   243  	REG_X13: 13,
   244  	REG_X14: 14,
   245  	REG_X15: 15,
   246  	REG_X16: 16,
   247  	REG_X17: 17,
   248  	REG_X18: 18,
   249  	REG_X19: 19,
   250  	REG_X20: 20,
   251  	REG_X21: 21,
   252  	REG_X22: 22,
   253  	REG_X23: 23,
   254  	REG_X24: 24,
   255  	REG_X25: 25,
   256  	REG_X26: 26,
   257  	REG_X27: 27,
   258  	REG_X28: 28,
   259  	REG_X29: 29,
   260  	REG_X30: 30,
   261  	REG_X31: 31,
   262  
   263  	// Floating-Point Registers.
   264  	REG_F0:  32,
   265  	REG_F1:  33,
   266  	REG_F2:  34,
   267  	REG_F3:  35,
   268  	REG_F4:  36,
   269  	REG_F5:  37,
   270  	REG_F6:  38,
   271  	REG_F7:  39,
   272  	REG_F8:  40,
   273  	REG_F9:  41,
   274  	REG_F10: 42,
   275  	REG_F11: 43,
   276  	REG_F12: 44,
   277  	REG_F13: 45,
   278  	REG_F14: 46,
   279  	REG_F15: 47,
   280  	REG_F16: 48,
   281  	REG_F17: 49,
   282  	REG_F18: 50,
   283  	REG_F19: 51,
   284  	REG_F20: 52,
   285  	REG_F21: 53,
   286  	REG_F22: 54,
   287  	REG_F23: 55,
   288  	REG_F24: 56,
   289  	REG_F25: 57,
   290  	REG_F26: 58,
   291  	REG_F27: 59,
   292  	REG_F28: 60,
   293  	REG_F29: 61,
   294  	REG_F30: 62,
   295  	REG_F31: 63,
   296  }
   297  
   298  // Prog.Mark flags.
   299  const (
   300  	// USES_REG_TMP indicates that a machine instruction generated from the
   301  	// corresponding *obj.Prog uses the temporary register.
   302  	USES_REG_TMP = 1 << iota
   303  
   304  	// NEED_JAL_RELOC is set on JAL instructions to indicate that a
   305  	// R_RISCV_JAL relocation is needed.
   306  	NEED_JAL_RELOC
   307  
   308  	// NEED_CALL_RELOC is set on an AUIPC instruction to indicate that it
   309  	// is the first instruction in an AUIPC + JAL pair that needs a
   310  	// R_RISCV_CALL relocation.
   311  	NEED_CALL_RELOC
   312  
   313  	// NEED_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that
   314  	// it is the first instruction in an AUIPC + I-type pair that needs a
   315  	// R_RISCV_PCREL_ITYPE relocation.
   316  	NEED_PCREL_ITYPE_RELOC
   317  
   318  	// NEED_PCREL_STYPE_RELOC is set on AUIPC instructions to indicate that
   319  	// it is the first instruction in an AUIPC + S-type pair that needs a
   320  	// R_RISCV_PCREL_STYPE relocation.
   321  	NEED_PCREL_STYPE_RELOC
   322  
   323  	// NEED_GOT_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that
   324  	// it is the first instruction in an AUIPC + I-type pair that needs a
   325  	// R_RISCV_GOT_PCREL_ITYPE relocation.
   326  	NEED_GOT_PCREL_ITYPE_RELOC
   327  )
   328  
   329  const NEED_RELOC = NEED_JAL_RELOC | NEED_CALL_RELOC | NEED_PCREL_ITYPE_RELOC |
   330  	NEED_PCREL_STYPE_RELOC | NEED_GOT_PCREL_ITYPE_RELOC
   331  
   332  // RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files
   333  // at https://github.com/riscv/riscv-opcodes.
   334  //
   335  // As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler.
   336  //
   337  // See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/.
   338  //
   339  // If you modify this table, you MUST run 'go generate' to regenerate anames.go!
   340  const (
   341  	//
   342  	// Unprivileged ISA (version 20240411)
   343  	//
   344  
   345  	// 2.4: Integer Computational Instructions
   346  	AADDI = obj.ABaseRISCV + obj.A_ARCHSPECIFIC + iota
   347  	ASLTI
   348  	ASLTIU
   349  	AANDI
   350  	AORI
   351  	AXORI
   352  	ASLLI
   353  	ASRLI
   354  	ASRAI
   355  	ALUI
   356  	AAUIPC
   357  	AADD
   358  	ASLT
   359  	ASLTU
   360  	AAND
   361  	AOR
   362  	AXOR
   363  	ASLL
   364  	ASRL
   365  	ASUB
   366  	ASRA
   367  
   368  	// 2.5: Control Transfer Instructions
   369  	AJAL
   370  	AJALR
   371  	ABEQ
   372  	ABNE
   373  	ABLT
   374  	ABLTU
   375  	ABGE
   376  	ABGEU
   377  
   378  	// 2.6: Load and Store Instructions
   379  	ALW
   380  	ALWU
   381  	ALH
   382  	ALHU
   383  	ALB
   384  	ALBU
   385  	ASW
   386  	ASH
   387  	ASB
   388  
   389  	// 2.7: Memory Ordering Instructions
   390  	AFENCE
   391  
   392  	// 4.2: Integer Computational Instructions (RV64I)
   393  	AADDIW
   394  	ASLLIW
   395  	ASRLIW
   396  	ASRAIW
   397  	AADDW
   398  	ASLLW
   399  	ASRLW
   400  	ASUBW
   401  	ASRAW
   402  
   403  	// 4.3: Load and Store Instructions (RV64I)
   404  	ALD
   405  	ASD
   406  
   407  	// 7.1: CSR Instructions (Zicsr)
   408  	ACSRRW
   409  	ACSRRS
   410  	ACSRRC
   411  	ACSRRWI
   412  	ACSRRSI
   413  	ACSRRCI
   414  
   415  	// 12.3: Integer Conditional Operations (Zicond)
   416  	ACZEROEQZ
   417  	ACZERONEZ
   418  
   419  	// 13.1: Multiplication Operations
   420  	AMUL
   421  	AMULH
   422  	AMULHU
   423  	AMULHSU
   424  	AMULW
   425  
   426  	// 13.2: Division Operations
   427  	ADIV
   428  	ADIVU
   429  	AREM
   430  	AREMU
   431  	ADIVW
   432  	ADIVUW
   433  	AREMW
   434  	AREMUW
   435  
   436  	// 14.2: Load-Reserved/Store-Conditional Instructions (Zalrsc)
   437  	ALRD
   438  	ASCD
   439  	ALRW
   440  	ASCW
   441  
   442  	// 14.4: Atomic Memory Operations (Zaamo)
   443  	AAMOSWAPD
   444  	AAMOADDD
   445  	AAMOANDD
   446  	AAMOORD
   447  	AAMOXORD
   448  	AAMOMAXD
   449  	AAMOMAXUD
   450  	AAMOMIND
   451  	AAMOMINUD
   452  	AAMOSWAPW
   453  	AAMOADDW
   454  	AAMOANDW
   455  	AAMOORW
   456  	AAMOXORW
   457  	AAMOMAXW
   458  	AAMOMAXUW
   459  	AAMOMINW
   460  	AAMOMINUW
   461  
   462  	// 20.5: Single-Precision Load and Store Instructions
   463  	AFLW
   464  	AFSW
   465  
   466  	// 20.6: Single-Precision Floating-Point Computational Instructions
   467  	AFADDS
   468  	AFSUBS
   469  	AFMULS
   470  	AFDIVS
   471  	AFMINS
   472  	AFMAXS
   473  	AFSQRTS
   474  	AFMADDS
   475  	AFMSUBS
   476  	AFNMADDS
   477  	AFNMSUBS
   478  
   479  	// 20.7: Single-Precision Floating-Point Conversion and Move Instructions
   480  	AFCVTWS
   481  	AFCVTLS
   482  	AFCVTSW
   483  	AFCVTSL
   484  	AFCVTWUS
   485  	AFCVTLUS
   486  	AFCVTSWU
   487  	AFCVTSLU
   488  	AFSGNJS
   489  	AFSGNJNS
   490  	AFSGNJXS
   491  	AFMVXS
   492  	AFMVSX
   493  	AFMVXW
   494  	AFMVWX
   495  
   496  	// 20.8: Single-Precision Floating-Point Compare Instructions
   497  	AFEQS
   498  	AFLTS
   499  	AFLES
   500  
   501  	// 20.9: Single-Precision Floating-Point Classify Instruction
   502  	AFCLASSS
   503  
   504  	// 21.3: Double-Precision Load and Store Instructions
   505  	AFLD
   506  	AFSD
   507  
   508  	// 21.4: Double-Precision Floating-Point Computational Instructions
   509  	AFADDD
   510  	AFSUBD
   511  	AFMULD
   512  	AFDIVD
   513  	AFMIND
   514  	AFMAXD
   515  	AFSQRTD
   516  	AFMADDD
   517  	AFMSUBD
   518  	AFNMADDD
   519  	AFNMSUBD
   520  
   521  	// 21.5: Double-Precision Floating-Point Conversion and Move Instructions
   522  	AFCVTWD
   523  	AFCVTLD
   524  	AFCVTDW
   525  	AFCVTDL
   526  	AFCVTWUD
   527  	AFCVTLUD
   528  	AFCVTDWU
   529  	AFCVTDLU
   530  	AFCVTSD
   531  	AFCVTDS
   532  	AFSGNJD
   533  	AFSGNJND
   534  	AFSGNJXD
   535  	AFMVXD
   536  	AFMVDX
   537  
   538  	// 21.6: Double-Precision Floating-Point Compare Instructions
   539  	AFEQD
   540  	AFLTD
   541  	AFLED
   542  
   543  	// 21.7: Double-Precision Floating-Point Classify Instruction
   544  	AFCLASSD
   545  
   546  	// 22.1 Quad-Precision Load and Store Instructions
   547  	AFLQ
   548  	AFSQ
   549  
   550  	// 22.2: Quad-Precision Computational Instructions
   551  	AFADDQ
   552  	AFSUBQ
   553  	AFMULQ
   554  	AFDIVQ
   555  	AFMINQ
   556  	AFMAXQ
   557  	AFSQRTQ
   558  	AFMADDQ
   559  	AFMSUBQ
   560  	AFNMADDQ
   561  	AFNMSUBQ
   562  
   563  	// 22.3: Quad-Precision Convert and Move Instructions
   564  	AFCVTWQ
   565  	AFCVTLQ
   566  	AFCVTSQ
   567  	AFCVTDQ
   568  	AFCVTQW
   569  	AFCVTQL
   570  	AFCVTQS
   571  	AFCVTQD
   572  	AFCVTWUQ
   573  	AFCVTLUQ
   574  	AFCVTQWU
   575  	AFCVTQLU
   576  	AFSGNJQ
   577  	AFSGNJNQ
   578  	AFSGNJXQ
   579  
   580  	// 22.4: Quad-Precision Floating-Point Compare Instructions
   581  	AFEQQ
   582  	AFLEQ
   583  	AFLTQ
   584  
   585  	// 22.5: Quad-Precision Floating-Point Classify Instruction
   586  	AFCLASSQ
   587  
   588  	//
   589  	// "C" Extension for Compressed Instructions
   590  	//
   591  
   592  	// 26.3.1: Compressed Stack-Pointer-Based Loads and Stores
   593  	ACLWSP
   594  	ACLDSP
   595  	ACFLDSP
   596  	ACSWSP
   597  	ACSDSP
   598  	ACFSDSP
   599  
   600  	// 26.3.2: Compressed Register-Based Loads and Stores
   601  	ACLW
   602  	ACLD
   603  	ACFLD
   604  	ACSW
   605  	ACSD
   606  	ACFSD
   607  
   608  	// 26.4: Compressed Control Transfer Instructions
   609  	ACJ
   610  	ACJR
   611  	ACJALR
   612  	ACBEQZ
   613  	ACBNEZ
   614  
   615  	// 26.5.1: Compressed Integer Constant-Generation Instructions
   616  	ACLI
   617  	ACLUI
   618  	ACADDI
   619  	ACADDIW
   620  	ACADDI16SP
   621  	ACADDI4SPN
   622  	ACSLLI
   623  	ACSRLI
   624  	ACSRAI
   625  	ACANDI
   626  
   627  	// 26.5.3: Compressed Integer Register-Register Operations
   628  	ACMV
   629  	ACADD
   630  	ACAND
   631  	ACOR
   632  	ACXOR
   633  	ACSUB
   634  	ACADDW
   635  	ACSUBW
   636  
   637  	// 26.5.5: Compressed NOP Instruction
   638  	ACNOP
   639  
   640  	// 26.5.6: Compressed Breakpoint Instruction
   641  	ACEBREAK
   642  
   643  	//
   644  	// "B" Extension for Bit Manipulation, Version 1.0.0
   645  	//
   646  
   647  	// 28.4.1: Address Generation Instructions (Zba)
   648  	AADDUW
   649  	ASH1ADD
   650  	ASH1ADDUW
   651  	ASH2ADD
   652  	ASH2ADDUW
   653  	ASH3ADD
   654  	ASH3ADDUW
   655  	ASLLIUW
   656  
   657  	// 28.4.2: Basic Bit Manipulation (Zbb)
   658  	AANDN
   659  	AORN
   660  	AXNOR
   661  	ACLZ
   662  	ACLZW
   663  	ACTZ
   664  	ACTZW
   665  	ACPOP
   666  	ACPOPW
   667  	AMAX
   668  	AMAXU
   669  	AMIN
   670  	AMINU
   671  	ASEXTB
   672  	ASEXTH
   673  	AZEXTH
   674  
   675  	// 28.4.2: Bitwise Rotation (Zbb)
   676  	AROL
   677  	AROLW
   678  	AROR
   679  	ARORI
   680  	ARORIW
   681  	ARORW
   682  	AORCB
   683  	AREV8
   684  
   685  	// 28.4.3: Carry-less multiplication (Zbc)
   686  	ACLMUL
   687  	ACLMULH
   688  	ACLMULR
   689  
   690  	// 28.4.4: Single-bit Instructions (Zbs)
   691  	ABCLR
   692  	ABCLRI
   693  	ABEXT
   694  	ABEXTI
   695  	ABINV
   696  	ABINVI
   697  	ABSET
   698  	ABSETI
   699  
   700  	//
   701  	// "V" Standard Extension for Vector Operations, Version 1.0
   702  	//
   703  
   704  	// 31.6: Configuration-Setting Instructions
   705  	AVSETVLI
   706  	AVSETIVLI
   707  	AVSETVL
   708  
   709  	// 31.7.4: Vector Unit-Stride Instructions
   710  	AVLE8V
   711  	AVLE16V
   712  	AVLE32V
   713  	AVLE64V
   714  	AVSE8V
   715  	AVSE16V
   716  	AVSE32V
   717  	AVSE64V
   718  	AVLMV
   719  	AVSMV
   720  
   721  	// 31.7.5: Vector Strided Instructions
   722  	AVLSE8V
   723  	AVLSE16V
   724  	AVLSE32V
   725  	AVLSE64V
   726  	AVSSE8V
   727  	AVSSE16V
   728  	AVSSE32V
   729  	AVSSE64V
   730  
   731  	// 31.7.6: Vector Indexed Instructions
   732  	AVLUXEI8V
   733  	AVLUXEI16V
   734  	AVLUXEI32V
   735  	AVLUXEI64V
   736  	AVLOXEI8V
   737  	AVLOXEI16V
   738  	AVLOXEI32V
   739  	AVLOXEI64V
   740  	AVSUXEI8V
   741  	AVSUXEI16V
   742  	AVSUXEI32V
   743  	AVSUXEI64V
   744  	AVSOXEI8V
   745  	AVSOXEI16V
   746  	AVSOXEI32V
   747  	AVSOXEI64V
   748  
   749  	// 31.7.7: Unit-stride Fault-Only-First Loads
   750  	AVLE8FFV
   751  	AVLE16FFV
   752  	AVLE32FFV
   753  	AVLE64FFV
   754  
   755  	// 31.7.8. Vector Load/Store Segment Instructions
   756  
   757  	// 31.7.8.1. Vector Unit-Stride Segment Loads and Stores
   758  	AVLSEG2E8V
   759  	AVLSEG3E8V
   760  	AVLSEG4E8V
   761  	AVLSEG5E8V
   762  	AVLSEG6E8V
   763  	AVLSEG7E8V
   764  	AVLSEG8E8V
   765  	AVLSEG2E16V
   766  	AVLSEG3E16V
   767  	AVLSEG4E16V
   768  	AVLSEG5E16V
   769  	AVLSEG6E16V
   770  	AVLSEG7E16V
   771  	AVLSEG8E16V
   772  	AVLSEG2E32V
   773  	AVLSEG3E32V
   774  	AVLSEG4E32V
   775  	AVLSEG5E32V
   776  	AVLSEG6E32V
   777  	AVLSEG7E32V
   778  	AVLSEG8E32V
   779  	AVLSEG2E64V
   780  	AVLSEG3E64V
   781  	AVLSEG4E64V
   782  	AVLSEG5E64V
   783  	AVLSEG6E64V
   784  	AVLSEG7E64V
   785  	AVLSEG8E64V
   786  
   787  	AVSSEG2E8V
   788  	AVSSEG3E8V
   789  	AVSSEG4E8V
   790  	AVSSEG5E8V
   791  	AVSSEG6E8V
   792  	AVSSEG7E8V
   793  	AVSSEG8E8V
   794  	AVSSEG2E16V
   795  	AVSSEG3E16V
   796  	AVSSEG4E16V
   797  	AVSSEG5E16V
   798  	AVSSEG6E16V
   799  	AVSSEG7E16V
   800  	AVSSEG8E16V
   801  	AVSSEG2E32V
   802  	AVSSEG3E32V
   803  	AVSSEG4E32V
   804  	AVSSEG5E32V
   805  	AVSSEG6E32V
   806  	AVSSEG7E32V
   807  	AVSSEG8E32V
   808  	AVSSEG2E64V
   809  	AVSSEG3E64V
   810  	AVSSEG4E64V
   811  	AVSSEG5E64V
   812  	AVSSEG6E64V
   813  	AVSSEG7E64V
   814  	AVSSEG8E64V
   815  
   816  	AVLSEG2E8FFV
   817  	AVLSEG3E8FFV
   818  	AVLSEG4E8FFV
   819  	AVLSEG5E8FFV
   820  	AVLSEG6E8FFV
   821  	AVLSEG7E8FFV
   822  	AVLSEG8E8FFV
   823  	AVLSEG2E16FFV
   824  	AVLSEG3E16FFV
   825  	AVLSEG4E16FFV
   826  	AVLSEG5E16FFV
   827  	AVLSEG6E16FFV
   828  	AVLSEG7E16FFV
   829  	AVLSEG8E16FFV
   830  	AVLSEG2E32FFV
   831  	AVLSEG3E32FFV
   832  	AVLSEG4E32FFV
   833  	AVLSEG5E32FFV
   834  	AVLSEG6E32FFV
   835  	AVLSEG7E32FFV
   836  	AVLSEG8E32FFV
   837  	AVLSEG2E64FFV
   838  	AVLSEG3E64FFV
   839  	AVLSEG4E64FFV
   840  	AVLSEG5E64FFV
   841  	AVLSEG6E64FFV
   842  	AVLSEG7E64FFV
   843  	AVLSEG8E64FFV
   844  
   845  	// 31.7.8.2. Vector Strided Segment Loads and Stores
   846  	AVLSSEG2E8V
   847  	AVLSSEG3E8V
   848  	AVLSSEG4E8V
   849  	AVLSSEG5E8V
   850  	AVLSSEG6E8V
   851  	AVLSSEG7E8V
   852  	AVLSSEG8E8V
   853  	AVLSSEG2E16V
   854  	AVLSSEG3E16V
   855  	AVLSSEG4E16V
   856  	AVLSSEG5E16V
   857  	AVLSSEG6E16V
   858  	AVLSSEG7E16V
   859  	AVLSSEG8E16V
   860  	AVLSSEG2E32V
   861  	AVLSSEG3E32V
   862  	AVLSSEG4E32V
   863  	AVLSSEG5E32V
   864  	AVLSSEG6E32V
   865  	AVLSSEG7E32V
   866  	AVLSSEG8E32V
   867  	AVLSSEG2E64V
   868  	AVLSSEG3E64V
   869  	AVLSSEG4E64V
   870  	AVLSSEG5E64V
   871  	AVLSSEG6E64V
   872  	AVLSSEG7E64V
   873  	AVLSSEG8E64V
   874  
   875  	AVSSSEG2E8V
   876  	AVSSSEG3E8V
   877  	AVSSSEG4E8V
   878  	AVSSSEG5E8V
   879  	AVSSSEG6E8V
   880  	AVSSSEG7E8V
   881  	AVSSSEG8E8V
   882  	AVSSSEG2E16V
   883  	AVSSSEG3E16V
   884  	AVSSSEG4E16V
   885  	AVSSSEG5E16V
   886  	AVSSSEG6E16V
   887  	AVSSSEG7E16V
   888  	AVSSSEG8E16V
   889  	AVSSSEG2E32V
   890  	AVSSSEG3E32V
   891  	AVSSSEG4E32V
   892  	AVSSSEG5E32V
   893  	AVSSSEG6E32V
   894  	AVSSSEG7E32V
   895  	AVSSSEG8E32V
   896  	AVSSSEG2E64V
   897  	AVSSSEG3E64V
   898  	AVSSSEG4E64V
   899  	AVSSSEG5E64V
   900  	AVSSSEG6E64V
   901  	AVSSSEG7E64V
   902  	AVSSSEG8E64V
   903  
   904  	// 31.7.8.3. Vector Indexed Segment Loads and Stores
   905  	AVLOXSEG2EI8V
   906  	AVLOXSEG3EI8V
   907  	AVLOXSEG4EI8V
   908  	AVLOXSEG5EI8V
   909  	AVLOXSEG6EI8V
   910  	AVLOXSEG7EI8V
   911  	AVLOXSEG8EI8V
   912  	AVLOXSEG2EI16V
   913  	AVLOXSEG3EI16V
   914  	AVLOXSEG4EI16V
   915  	AVLOXSEG5EI16V
   916  	AVLOXSEG6EI16V
   917  	AVLOXSEG7EI16V
   918  	AVLOXSEG8EI16V
   919  	AVLOXSEG2EI32V
   920  	AVLOXSEG3EI32V
   921  	AVLOXSEG4EI32V
   922  	AVLOXSEG5EI32V
   923  	AVLOXSEG6EI32V
   924  	AVLOXSEG7EI32V
   925  	AVLOXSEG8EI32V
   926  	AVLOXSEG2EI64V
   927  	AVLOXSEG3EI64V
   928  	AVLOXSEG4EI64V
   929  	AVLOXSEG5EI64V
   930  	AVLOXSEG6EI64V
   931  	AVLOXSEG7EI64V
   932  	AVLOXSEG8EI64V
   933  
   934  	AVSOXSEG2EI8V
   935  	AVSOXSEG3EI8V
   936  	AVSOXSEG4EI8V
   937  	AVSOXSEG5EI8V
   938  	AVSOXSEG6EI8V
   939  	AVSOXSEG7EI8V
   940  	AVSOXSEG8EI8V
   941  	AVSOXSEG2EI16V
   942  	AVSOXSEG3EI16V
   943  	AVSOXSEG4EI16V
   944  	AVSOXSEG5EI16V
   945  	AVSOXSEG6EI16V
   946  	AVSOXSEG7EI16V
   947  	AVSOXSEG8EI16V
   948  	AVSOXSEG2EI32V
   949  	AVSOXSEG3EI32V
   950  	AVSOXSEG4EI32V
   951  	AVSOXSEG5EI32V
   952  	AVSOXSEG6EI32V
   953  	AVSOXSEG7EI32V
   954  	AVSOXSEG8EI32V
   955  	AVSOXSEG2EI64V
   956  	AVSOXSEG3EI64V
   957  	AVSOXSEG4EI64V
   958  	AVSOXSEG5EI64V
   959  	AVSOXSEG6EI64V
   960  	AVSOXSEG7EI64V
   961  	AVSOXSEG8EI64V
   962  
   963  	AVLUXSEG2EI8V
   964  	AVLUXSEG3EI8V
   965  	AVLUXSEG4EI8V
   966  	AVLUXSEG5EI8V
   967  	AVLUXSEG6EI8V
   968  	AVLUXSEG7EI8V
   969  	AVLUXSEG8EI8V
   970  	AVLUXSEG2EI16V
   971  	AVLUXSEG3EI16V
   972  	AVLUXSEG4EI16V
   973  	AVLUXSEG5EI16V
   974  	AVLUXSEG6EI16V
   975  	AVLUXSEG7EI16V
   976  	AVLUXSEG8EI16V
   977  	AVLUXSEG2EI32V
   978  	AVLUXSEG3EI32V
   979  	AVLUXSEG4EI32V
   980  	AVLUXSEG5EI32V
   981  	AVLUXSEG6EI32V
   982  	AVLUXSEG7EI32V
   983  	AVLUXSEG8EI32V
   984  	AVLUXSEG2EI64V
   985  	AVLUXSEG3EI64V
   986  	AVLUXSEG4EI64V
   987  	AVLUXSEG5EI64V
   988  	AVLUXSEG6EI64V
   989  	AVLUXSEG7EI64V
   990  	AVLUXSEG8EI64V
   991  
   992  	AVSUXSEG2EI8V
   993  	AVSUXSEG3EI8V
   994  	AVSUXSEG4EI8V
   995  	AVSUXSEG5EI8V
   996  	AVSUXSEG6EI8V
   997  	AVSUXSEG7EI8V
   998  	AVSUXSEG8EI8V
   999  	AVSUXSEG2EI16V
  1000  	AVSUXSEG3EI16V
  1001  	AVSUXSEG4EI16V
  1002  	AVSUXSEG5EI16V
  1003  	AVSUXSEG6EI16V
  1004  	AVSUXSEG7EI16V
  1005  	AVSUXSEG8EI16V
  1006  	AVSUXSEG2EI32V
  1007  	AVSUXSEG3EI32V
  1008  	AVSUXSEG4EI32V
  1009  	AVSUXSEG5EI32V
  1010  	AVSUXSEG6EI32V
  1011  	AVSUXSEG7EI32V
  1012  	AVSUXSEG8EI32V
  1013  	AVSUXSEG2EI64V
  1014  	AVSUXSEG3EI64V
  1015  	AVSUXSEG4EI64V
  1016  	AVSUXSEG5EI64V
  1017  	AVSUXSEG6EI64V
  1018  	AVSUXSEG7EI64V
  1019  	AVSUXSEG8EI64V
  1020  
  1021  	// 31.7.9: Vector Load/Store Whole Register Instructions
  1022  	AVL1RE8V
  1023  	AVL1RE16V
  1024  	AVL1RE32V
  1025  	AVL1RE64V
  1026  	AVL2RE8V
  1027  	AVL2RE16V
  1028  	AVL2RE32V
  1029  	AVL2RE64V
  1030  	AVL4RE8V
  1031  	AVL4RE16V
  1032  	AVL4RE32V
  1033  	AVL4RE64V
  1034  	AVL8RE8V
  1035  	AVL8RE16V
  1036  	AVL8RE32V
  1037  	AVL8RE64V
  1038  	AVS1RV
  1039  	AVS2RV
  1040  	AVS4RV
  1041  	AVS8RV
  1042  
  1043  	// 31.11.1: Vector Single-Width Integer Add and Subtract
  1044  	AVADDVV
  1045  	AVADDVX
  1046  	AVADDVI
  1047  	AVSUBVV
  1048  	AVSUBVX
  1049  	AVRSUBVX
  1050  	AVRSUBVI
  1051  
  1052  	// 31.11.2: Vector Widening Integer Add/Subtract
  1053  	AVWADDUVV
  1054  	AVWADDUVX
  1055  	AVWSUBUVV
  1056  	AVWSUBUVX
  1057  	AVWADDVV
  1058  	AVWADDVX
  1059  	AVWSUBVV
  1060  	AVWSUBVX
  1061  	AVWADDUWV
  1062  	AVWADDUWX
  1063  	AVWSUBUWV
  1064  	AVWSUBUWX
  1065  	AVWADDWV
  1066  	AVWADDWX
  1067  	AVWSUBWV
  1068  	AVWSUBWX
  1069  
  1070  	// 31.11.3: Vector Integer Extension
  1071  	AVZEXTVF2
  1072  	AVSEXTVF2
  1073  	AVZEXTVF4
  1074  	AVSEXTVF4
  1075  	AVZEXTVF8
  1076  	AVSEXTVF8
  1077  
  1078  	// 31.11.4: Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
  1079  	AVADCVVM
  1080  	AVADCVXM
  1081  	AVADCVIM
  1082  	AVMADCVVM
  1083  	AVMADCVXM
  1084  	AVMADCVIM
  1085  	AVMADCVV
  1086  	AVMADCVX
  1087  	AVMADCVI
  1088  	AVSBCVVM
  1089  	AVSBCVXM
  1090  	AVMSBCVVM
  1091  	AVMSBCVXM
  1092  	AVMSBCVV
  1093  	AVMSBCVX
  1094  
  1095  	// 31.11.5: Vector Bitwise Logical Instructions
  1096  	AVANDVV
  1097  	AVANDVX
  1098  	AVANDVI
  1099  	AVORVV
  1100  	AVORVX
  1101  	AVORVI
  1102  	AVXORVV
  1103  	AVXORVX
  1104  	AVXORVI
  1105  
  1106  	// 31.11.6: Vector Single-Width Shift Instructions
  1107  	AVSLLVV
  1108  	AVSLLVX
  1109  	AVSLLVI
  1110  	AVSRLVV
  1111  	AVSRLVX
  1112  	AVSRLVI
  1113  	AVSRAVV
  1114  	AVSRAVX
  1115  	AVSRAVI
  1116  
  1117  	// 31.11.7: Vector Narrowing Integer Right Shift Instructions
  1118  	AVNSRLWV
  1119  	AVNSRLWX
  1120  	AVNSRLWI
  1121  	AVNSRAWV
  1122  	AVNSRAWX
  1123  	AVNSRAWI
  1124  
  1125  	// 31.11.8: Vector Integer Compare Instructions
  1126  	AVMSEQVV
  1127  	AVMSEQVX
  1128  	AVMSEQVI
  1129  	AVMSNEVV
  1130  	AVMSNEVX
  1131  	AVMSNEVI
  1132  	AVMSLTUVV
  1133  	AVMSLTUVX
  1134  	AVMSLTVV
  1135  	AVMSLTVX
  1136  	AVMSLEUVV
  1137  	AVMSLEUVX
  1138  	AVMSLEUVI
  1139  	AVMSLEVV
  1140  	AVMSLEVX
  1141  	AVMSLEVI
  1142  	AVMSGTUVX
  1143  	AVMSGTUVI
  1144  	AVMSGTVX
  1145  	AVMSGTVI
  1146  
  1147  	// 31.11.9: Vector Integer Min/Max Instructions
  1148  	AVMINUVV
  1149  	AVMINUVX
  1150  	AVMINVV
  1151  	AVMINVX
  1152  	AVMAXUVV
  1153  	AVMAXUVX
  1154  	AVMAXVV
  1155  	AVMAXVX
  1156  
  1157  	// 31.11.10: Vector Single-Width Integer Multiply Instructions
  1158  	AVMULVV
  1159  	AVMULVX
  1160  	AVMULHVV
  1161  	AVMULHVX
  1162  	AVMULHUVV
  1163  	AVMULHUVX
  1164  	AVMULHSUVV
  1165  	AVMULHSUVX
  1166  
  1167  	// 31.11.11: Vector Integer Divide Instructions
  1168  	AVDIVUVV
  1169  	AVDIVUVX
  1170  	AVDIVVV
  1171  	AVDIVVX
  1172  	AVREMUVV
  1173  	AVREMUVX
  1174  	AVREMVV
  1175  	AVREMVX
  1176  
  1177  	// 31.11.12: Vector Widening Integer Multiply Instructions
  1178  	AVWMULVV
  1179  	AVWMULVX
  1180  	AVWMULUVV
  1181  	AVWMULUVX
  1182  	AVWMULSUVV
  1183  	AVWMULSUVX
  1184  
  1185  	// 31.11.13: Vector Single-Width Integer Multiply-Add Instructions
  1186  	AVMACCVV
  1187  	AVMACCVX
  1188  	AVNMSACVV
  1189  	AVNMSACVX
  1190  	AVMADDVV
  1191  	AVMADDVX
  1192  	AVNMSUBVV
  1193  	AVNMSUBVX
  1194  
  1195  	// 31.11.14: Vector Widening Integer Multiply-Add Instructions
  1196  	AVWMACCUVV
  1197  	AVWMACCUVX
  1198  	AVWMACCVV
  1199  	AVWMACCVX
  1200  	AVWMACCSUVV
  1201  	AVWMACCSUVX
  1202  	AVWMACCUSVX
  1203  
  1204  	// 31.11.15: Vector Integer Merge Instructions
  1205  	AVMERGEVVM
  1206  	AVMERGEVXM
  1207  	AVMERGEVIM
  1208  
  1209  	// 31.11.16: Vector Integer Move Instructions
  1210  	AVMVVV
  1211  	AVMVVX
  1212  	AVMVVI
  1213  
  1214  	// 31.12.1: Vector Single-Width Saturating Add and Subtract
  1215  	AVSADDUVV
  1216  	AVSADDUVX
  1217  	AVSADDUVI
  1218  	AVSADDVV
  1219  	AVSADDVX
  1220  	AVSADDVI
  1221  	AVSSUBUVV
  1222  	AVSSUBUVX
  1223  	AVSSUBVV
  1224  	AVSSUBVX
  1225  
  1226  	// 31.12.2: Vector Single-Width Averaging Add and Subtract
  1227  	AVAADDUVV
  1228  	AVAADDUVX
  1229  	AVAADDVV
  1230  	AVAADDVX
  1231  	AVASUBUVV
  1232  	AVASUBUVX
  1233  	AVASUBVV
  1234  	AVASUBVX
  1235  
  1236  	// 31.12.3: Vector Single-Width Fractional Multiply with Rounding and Saturation
  1237  	AVSMULVV
  1238  	AVSMULVX
  1239  
  1240  	// 31.12.4: Vector Single-Width Scaling Shift Instructions
  1241  	AVSSRLVV
  1242  	AVSSRLVX
  1243  	AVSSRLVI
  1244  	AVSSRAVV
  1245  	AVSSRAVX
  1246  	AVSSRAVI
  1247  
  1248  	// 31.12.5: Vector Narrowing Fixed-Point Clip Instructions
  1249  	AVNCLIPUWV
  1250  	AVNCLIPUWX
  1251  	AVNCLIPUWI
  1252  	AVNCLIPWV
  1253  	AVNCLIPWX
  1254  	AVNCLIPWI
  1255  
  1256  	// 31.13.2: Vector Single-Width Floating-Point Add/Subtract Instructions
  1257  	AVFADDVV
  1258  	AVFADDVF
  1259  	AVFSUBVV
  1260  	AVFSUBVF
  1261  	AVFRSUBVF
  1262  
  1263  	// 31.13.3: Vector Widening Floating-Point Add/Subtract Instructions
  1264  	AVFWADDVV
  1265  	AVFWADDVF
  1266  	AVFWSUBVV
  1267  	AVFWSUBVF
  1268  	AVFWADDWV
  1269  	AVFWADDWF
  1270  	AVFWSUBWV
  1271  	AVFWSUBWF
  1272  
  1273  	// 31.13.4: Vector Single-Width Floating-Point Multiply/Divide Instructions
  1274  	AVFMULVV
  1275  	AVFMULVF
  1276  	AVFDIVVV
  1277  	AVFDIVVF
  1278  	AVFRDIVVF
  1279  
  1280  	// 31.13.5: Vector Widening Floating-Point Multiply
  1281  	AVFWMULVV
  1282  	AVFWMULVF
  1283  
  1284  	// 31.13.6: Vector Single-Width Floating-Point Fused Multiply-Add Instructions
  1285  	AVFMACCVV
  1286  	AVFMACCVF
  1287  	AVFNMACCVV
  1288  	AVFNMACCVF
  1289  	AVFMSACVV
  1290  	AVFMSACVF
  1291  	AVFNMSACVV
  1292  	AVFNMSACVF
  1293  	AVFMADDVV
  1294  	AVFMADDVF
  1295  	AVFNMADDVV
  1296  	AVFNMADDVF
  1297  	AVFMSUBVV
  1298  	AVFMSUBVF
  1299  	AVFNMSUBVV
  1300  	AVFNMSUBVF
  1301  
  1302  	// 31.13.7: Vector Widening Floating-Point Fused Multiply-Add Instructions
  1303  	AVFWMACCVV
  1304  	AVFWMACCVF
  1305  	AVFWNMACCVV
  1306  	AVFWNMACCVF
  1307  	AVFWMSACVV
  1308  	AVFWMSACVF
  1309  	AVFWNMSACVV
  1310  	AVFWNMSACVF
  1311  
  1312  	// 31.13.8: Vector Floating-Point Square-Root Instruction
  1313  	AVFSQRTV
  1314  
  1315  	// 31.13.9: Vector Floating-Point Reciprocal Square-Root Estimate Instruction
  1316  	AVFRSQRT7V
  1317  
  1318  	// 31.13.10: Vector Floating-Point Reciprocal Estimate Instruction
  1319  	AVFREC7V
  1320  
  1321  	// 31.13.11: Vector Floating-Point MIN/MAX Instructions
  1322  	AVFMINVV
  1323  	AVFMINVF
  1324  	AVFMAXVV
  1325  	AVFMAXVF
  1326  
  1327  	// 31.13.12: Vector Floating-Point Sign-Injection Instructions
  1328  	AVFSGNJVV
  1329  	AVFSGNJVF
  1330  	AVFSGNJNVV
  1331  	AVFSGNJNVF
  1332  	AVFSGNJXVV
  1333  	AVFSGNJXVF
  1334  
  1335  	// 31.13.13: Vector Floating-Point Compare Instructions
  1336  	AVMFEQVV
  1337  	AVMFEQVF
  1338  	AVMFNEVV
  1339  	AVMFNEVF
  1340  	AVMFLTVV
  1341  	AVMFLTVF
  1342  	AVMFLEVV
  1343  	AVMFLEVF
  1344  	AVMFGTVF
  1345  	AVMFGEVF
  1346  
  1347  	// 31.13.14: Vector Floating-Point Classify Instruction
  1348  	AVFCLASSV
  1349  
  1350  	// 31.13.15: Vector Floating-Point Merge Instruction
  1351  	AVFMERGEVFM
  1352  
  1353  	// 31.13.16: Vector Floating-Point Move Instruction
  1354  	AVFMVVF
  1355  
  1356  	// 31.13.17: Single-Width Floating-Point/Integer Type-Convert Instructions
  1357  	AVFCVTXUFV
  1358  	AVFCVTXFV
  1359  	AVFCVTRTZXUFV
  1360  	AVFCVTRTZXFV
  1361  	AVFCVTFXUV
  1362  	AVFCVTFXV
  1363  
  1364  	// 31.13.18: Widening Floating-Point/Integer Type-Convert Instructions
  1365  	AVFWCVTXUFV
  1366  	AVFWCVTXFV
  1367  	AVFWCVTRTZXUFV
  1368  	AVFWCVTRTZXFV
  1369  	AVFWCVTFXUV
  1370  	AVFWCVTFXV
  1371  	AVFWCVTFFV
  1372  
  1373  	// 31.13.19: Narrowing Floating-Point/Integer Type-Convert Instructions
  1374  	AVFNCVTXUFW
  1375  	AVFNCVTXFW
  1376  	AVFNCVTRTZXUFW
  1377  	AVFNCVTRTZXFW
  1378  	AVFNCVTFXUW
  1379  	AVFNCVTFXW
  1380  	AVFNCVTFFW
  1381  	AVFNCVTRODFFW
  1382  
  1383  	// 31.14.1: Vector Single-Width Integer Reduction Instructions
  1384  	AVREDSUMVS
  1385  	AVREDMAXUVS
  1386  	AVREDMAXVS
  1387  	AVREDMINUVS
  1388  	AVREDMINVS
  1389  	AVREDANDVS
  1390  	AVREDORVS
  1391  	AVREDXORVS
  1392  
  1393  	// 31.14.2: Vector Widening Integer Reduction Instructions
  1394  	AVWREDSUMUVS
  1395  	AVWREDSUMVS
  1396  
  1397  	// 31.14.3: Vector Single-Width Floating-Point Reduction Instructions
  1398  	AVFREDOSUMVS
  1399  	AVFREDUSUMVS
  1400  	AVFREDMAXVS
  1401  	AVFREDMINVS
  1402  
  1403  	// 31.14.4: Vector Widening Floating-Point Reduction Instructions
  1404  	AVFWREDOSUMVS
  1405  	AVFWREDUSUMVS
  1406  
  1407  	// 31.15: Vector Mask Instructions
  1408  	AVMANDMM
  1409  	AVMNANDMM
  1410  	AVMANDNMM
  1411  	AVMXORMM
  1412  	AVMORMM
  1413  	AVMNORMM
  1414  	AVMORNMM
  1415  	AVMXNORMM
  1416  	AVCPOPM
  1417  	AVFIRSTM
  1418  	AVMSBFM
  1419  	AVMSIFM
  1420  	AVMSOFM
  1421  	AVIOTAM
  1422  	AVIDV
  1423  
  1424  	// 31.16.1: Integer Scalar Move Instructions
  1425  	AVMVXS
  1426  	AVMVSX
  1427  
  1428  	// 31.16.2: Floating-Point Scalar Move Instructions
  1429  	AVFMVFS
  1430  	AVFMVSF
  1431  
  1432  	// 31.16.3: Vector Slide Instructions
  1433  	AVSLIDEUPVX
  1434  	AVSLIDEUPVI
  1435  	AVSLIDEDOWNVX
  1436  	AVSLIDEDOWNVI
  1437  	AVSLIDE1UPVX
  1438  	AVFSLIDE1UPVF
  1439  	AVSLIDE1DOWNVX
  1440  	AVFSLIDE1DOWNVF
  1441  
  1442  	// 31.16.4: Vector Register Gather Instructions
  1443  	AVRGATHERVV
  1444  	AVRGATHEREI16VV
  1445  	AVRGATHERVX
  1446  	AVRGATHERVI
  1447  
  1448  	// 31.16.5: Vector Compress Instruction
  1449  	AVCOMPRESSVM
  1450  
  1451  	// 31.16.6: Whole Vector Register Move
  1452  	AVMV1RV
  1453  	AVMV2RV
  1454  	AVMV4RV
  1455  	AVMV8RV
  1456  
  1457  	//
  1458  	// Privileged ISA (version 20240411)
  1459  	//
  1460  
  1461  	// 3.3.1: Environment Call and Breakpoint
  1462  	AECALL
  1463  	ASCALL
  1464  	AEBREAK
  1465  	ASBREAK
  1466  
  1467  	// 3.3.2: Trap-Return Instructions
  1468  	AMRET
  1469  	ASRET
  1470  	ADRET
  1471  
  1472  	// 3.3.3: Wait for Interrupt
  1473  	AWFI
  1474  
  1475  	// 10.2: Supervisor Memory-Management Fence Instruction
  1476  	ASFENCEVMA
  1477  
  1478  	// The escape hatch. Inserts a single 32-bit word.
  1479  	AWORD
  1480  
  1481  	// Pseudo-instructions.  These get translated by the assembler into other
  1482  	// instructions, based on their operands.
  1483  	ABEQZ
  1484  	ABGEZ
  1485  	ABGT
  1486  	ABGTU
  1487  	ABGTZ
  1488  	ABLE
  1489  	ABLEU
  1490  	ABLEZ
  1491  	ABLTZ
  1492  	ABNEZ
  1493  	AFABSD
  1494  	AFABSS
  1495  	AFNED
  1496  	AFNEGD
  1497  	AFNEGS
  1498  	AFNES
  1499  	AMOV
  1500  	AMOVB
  1501  	AMOVBU
  1502  	AMOVD
  1503  	AMOVF
  1504  	AMOVH
  1505  	AMOVHU
  1506  	AMOVW
  1507  	AMOVWU
  1508  	ANEG
  1509  	ANEGW
  1510  	ANOT
  1511  	APAUSE
  1512  	ARDCYCLE
  1513  	ARDINSTRET
  1514  	ARDTIME
  1515  	ASEQZ
  1516  	ASNEZ
  1517  	AVFABSV
  1518  	AVFNEGV
  1519  	AVL1RV
  1520  	AVL2RV
  1521  	AVL4RV
  1522  	AVL8RV
  1523  	AVMCLRM
  1524  	AVMFGEVV
  1525  	AVMFGTVV
  1526  	AVMMVM
  1527  	AVMNOTM
  1528  	AVMSETM
  1529  	AVMSGEUVI
  1530  	AVMSGEUVV
  1531  	AVMSGEVI
  1532  	AVMSGEVV
  1533  	AVMSGTUVV
  1534  	AVMSGTVV
  1535  	AVMSLTUVI
  1536  	AVMSLTVI
  1537  	AVNCVTXXW
  1538  	AVNEGV
  1539  	AVNOTV
  1540  	AVWCVTUXXV
  1541  	AVWCVTXXV
  1542  
  1543  	// End marker
  1544  	ALAST
  1545  )
  1546  
  1547  // opSuffix encoding to uint8 which fit into p.Scond
  1548  var rmSuffixSet = map[string]uint8{
  1549  	"RNE": RM_RNE,
  1550  	"RTZ": RM_RTZ,
  1551  	"RDN": RM_RDN,
  1552  	"RUP": RM_RUP,
  1553  	"RMM": RM_RMM,
  1554  }
  1555  
  1556  const (
  1557  	fenceTsoSuffixBit uint8 = 1 << 0
  1558  	rmSuffixBit       uint8 = 1 << 7
  1559  )
  1560  
  1561  func rmSuffixEncode(s string) (uint8, error) {
  1562  	if s == "" {
  1563  		return 0, errors.New("empty suffix")
  1564  	}
  1565  	enc, ok := rmSuffixSet[s]
  1566  	if !ok {
  1567  		return 0, fmt.Errorf("invalid encoding for unknown suffix:%q", s)
  1568  	}
  1569  	return enc | rmSuffixBit, nil
  1570  }
  1571  
  1572  func rmSuffixString(u uint8) (string, error) {
  1573  	if u&rmSuffixBit == 0 {
  1574  		return "", fmt.Errorf("invalid suffix, require round mode bit:%x", u)
  1575  	}
  1576  
  1577  	u &^= rmSuffixBit
  1578  	for k, v := range rmSuffixSet {
  1579  		if v == u {
  1580  			return k, nil
  1581  		}
  1582  	}
  1583  	return "", fmt.Errorf("unknown suffix:%x", u)
  1584  }
  1585  
  1586  const (
  1587  	RM_RNE uint8 = iota // Round to Nearest, ties to Even
  1588  	RM_RTZ              // Round towards Zero
  1589  	RM_RDN              // Round Down
  1590  	RM_RUP              // Round Up
  1591  	RM_RMM              // Round to Nearest, ties to Max Magnitude
  1592  )
  1593  
  1594  type SpecialOperand int
  1595  
  1596  const (
  1597  	SPOP_BEGIN SpecialOperand = obj.SpecialOperandRISCVBase
  1598  	SPOP_RVV_BEGIN
  1599  
  1600  	// Vector mask policy.
  1601  	SPOP_MA SpecialOperand = obj.SpecialOperandRISCVBase + iota - 2
  1602  	SPOP_MU
  1603  
  1604  	// Vector tail policy.
  1605  	SPOP_TA
  1606  	SPOP_TU
  1607  
  1608  	// Vector register group multiplier (VLMUL).
  1609  	SPOP_M1
  1610  	SPOP_M2
  1611  	SPOP_M4
  1612  	SPOP_M8
  1613  	SPOP_MF2
  1614  	SPOP_MF4
  1615  	SPOP_MF8
  1616  
  1617  	// Vector selected element width (VSEW).
  1618  	SPOP_E8
  1619  	SPOP_E16
  1620  	SPOP_E32
  1621  	SPOP_E64
  1622  	SPOP_RVV_END
  1623  
  1624  	// CSR names.  4096 special operands are reserved for RISC-V CSR names.
  1625  	SPOP_CSR_BEGIN = SPOP_RVV_END
  1626  	SPOP_CSR_END   = SPOP_CSR_BEGIN + 4096
  1627  
  1628  	// FENCE operands. 16 special operands are reserved for FENCE flags (4 bits: IORW).
  1629  	SPOP_FENCE_BEGIN = SPOP_CSR_END
  1630  
  1631  	SPOP_FENCE_W SpecialOperand = SPOP_FENCE_BEGIN + iota - 20
  1632  	SPOP_FENCE_R
  1633  	SPOP_FENCE_RW
  1634  	SPOP_FENCE_O
  1635  	SPOP_FENCE_OW
  1636  	SPOP_FENCE_OR
  1637  	SPOP_FENCE_ORW
  1638  	SPOP_FENCE_I
  1639  	SPOP_FENCE_IW
  1640  	SPOP_FENCE_IR
  1641  	SPOP_FENCE_IRW
  1642  	SPOP_FENCE_IO
  1643  	SPOP_FENCE_IOW
  1644  	SPOP_FENCE_IOR
  1645  	SPOP_FENCE_IORW
  1646  
  1647  	SPOP_FENCE_END = SPOP_FENCE_BEGIN + 16
  1648  
  1649  	SPOP_END = SPOP_FENCE_END + 1
  1650  )
  1651  
  1652  var specialOperands = map[SpecialOperand]struct {
  1653  	encoding uint32
  1654  	name     string
  1655  }{
  1656  	SPOP_MA: {encoding: 1, name: "MA"},
  1657  	SPOP_MU: {encoding: 0, name: "MU"},
  1658  
  1659  	SPOP_TA: {encoding: 1, name: "TA"},
  1660  	SPOP_TU: {encoding: 0, name: "TU"},
  1661  
  1662  	SPOP_M1:  {encoding: 0, name: "M1"},
  1663  	SPOP_M2:  {encoding: 1, name: "M2"},
  1664  	SPOP_M4:  {encoding: 2, name: "M4"},
  1665  	SPOP_M8:  {encoding: 3, name: "M8"},
  1666  	SPOP_MF8: {encoding: 5, name: "MF8"},
  1667  	SPOP_MF4: {encoding: 6, name: "MF4"},
  1668  	SPOP_MF2: {encoding: 7, name: "MF2"},
  1669  
  1670  	SPOP_E8:  {encoding: 0, name: "E8"},
  1671  	SPOP_E16: {encoding: 1, name: "E16"},
  1672  	SPOP_E32: {encoding: 2, name: "E32"},
  1673  	SPOP_E64: {encoding: 3, name: "E64"},
  1674  
  1675  	SPOP_FENCE_W:    {encoding: 1, name: "W"},
  1676  	SPOP_FENCE_R:    {encoding: 2, name: "R"},
  1677  	SPOP_FENCE_RW:   {encoding: 3, name: "RW"},
  1678  	SPOP_FENCE_O:    {encoding: 4, name: "O"},
  1679  	SPOP_FENCE_OW:   {encoding: 5, name: "OW"},
  1680  	SPOP_FENCE_OR:   {encoding: 6, name: "OR"},
  1681  	SPOP_FENCE_ORW:  {encoding: 7, name: "ORW"},
  1682  	SPOP_FENCE_I:    {encoding: 8, name: "I"},
  1683  	SPOP_FENCE_IW:   {encoding: 9, name: "IW"},
  1684  	SPOP_FENCE_IR:   {encoding: 10, name: "IR"},
  1685  	SPOP_FENCE_IRW:  {encoding: 11, name: "IRW"},
  1686  	SPOP_FENCE_IO:   {encoding: 12, name: "IO"},
  1687  	SPOP_FENCE_IOW:  {encoding: 13, name: "IOW"},
  1688  	SPOP_FENCE_IOR:  {encoding: 14, name: "IOR"},
  1689  	SPOP_FENCE_IORW: {encoding: 15, name: "IORW"},
  1690  }
  1691  
  1692  func (so SpecialOperand) encode() uint32 {
  1693  	switch {
  1694  	case so >= SPOP_RVV_BEGIN && so < SPOP_RVV_END:
  1695  		op, ok := specialOperands[so]
  1696  		if ok {
  1697  			return op.encoding
  1698  		}
  1699  	case so >= SPOP_CSR_BEGIN && so < SPOP_CSR_END:
  1700  		csrNum := uint16(so - SPOP_CSR_BEGIN)
  1701  		if _, ok := csrs[csrNum]; ok {
  1702  			return uint32(csrNum)
  1703  		}
  1704  	case so > SPOP_FENCE_BEGIN && so < SPOP_FENCE_END:
  1705  		op, ok := specialOperands[so]
  1706  		if ok {
  1707  			return op.encoding
  1708  		}
  1709  	}
  1710  	return 0
  1711  }
  1712  
  1713  // String returns the textual representation of a SpecialOperand.
  1714  func (so SpecialOperand) String() string {
  1715  	switch {
  1716  	case so >= SPOP_RVV_BEGIN && so < SPOP_RVV_END:
  1717  		op, ok := specialOperands[so]
  1718  		if ok {
  1719  			return op.name
  1720  		}
  1721  	case so >= SPOP_CSR_BEGIN && so < SPOP_CSR_END:
  1722  		if csrName, ok := csrs[uint16(so-SPOP_CSR_BEGIN)]; ok {
  1723  			return csrName
  1724  		}
  1725  	case so > SPOP_FENCE_BEGIN && so < SPOP_FENCE_END:
  1726  		op, ok := specialOperands[so]
  1727  		if ok {
  1728  			return op.name
  1729  		}
  1730  	}
  1731  	return ""
  1732  }
  1733  
  1734  // All unary instructions which write to their arguments (as opposed to reading
  1735  // from them) go here. The assembly parser uses this information to populate
  1736  // its AST in a semantically reasonable way.
  1737  //
  1738  // Any instructions not listed here are assumed to either be non-unary or to read
  1739  // from its argument.
  1740  var unaryDst = map[obj.As]bool{
  1741  	ARDCYCLE:   true,
  1742  	ARDTIME:    true,
  1743  	ARDINSTRET: true,
  1744  }
  1745  
  1746  // Instruction encoding masks.
  1747  const (
  1748  	// BTypeImmMask is a mask including only the immediate portion of
  1749  	// B-type instructions.
  1750  	BTypeImmMask = 0xfe000f80
  1751  
  1752  	// CBTypeImmMask is a mask including only the immediate portion of
  1753  	// CB-type instructions.
  1754  	CBTypeImmMask = 0x1c7c
  1755  
  1756  	// CJTypeImmMask is a mask including only the immediate portion of
  1757  	// CJ-type instructions.
  1758  	CJTypeImmMask = 0x1f7c
  1759  
  1760  	// ITypeImmMask is a mask including only the immediate portion of
  1761  	// I-type instructions.
  1762  	ITypeImmMask = 0xfff00000
  1763  
  1764  	// JTypeImmMask is a mask including only the immediate portion of
  1765  	// J-type instructions.
  1766  	JTypeImmMask = 0xfffff000
  1767  
  1768  	// STypeImmMask is a mask including only the immediate portion of
  1769  	// S-type instructions.
  1770  	STypeImmMask = 0xfe000f80
  1771  
  1772  	// UTypeImmMask is a mask including only the immediate portion of
  1773  	// U-type instructions.
  1774  	UTypeImmMask = 0xfffff000
  1775  )
  1776  

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