RISCV64Ops.go

     1  // Copyright 2016 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  package main
     6  
     7  import (
     8  	"fmt"
     9  )
    10  
    11  // Notes:
    12  //  - Boolean types occupy the entire register. 0=false, 1=true.
    13  
    14  // Suffixes encode the bit width of various instructions:
    15  //
    16  // D (double word) = 64 bit int
    17  // W (word)        = 32 bit int
    18  // H (half word)   = 16 bit int
    19  // B (byte)        = 8 bit int
    20  // S (single)      = 32 bit float
    21  // D (double)      = 64 bit float
    22  // L               = 64 bit int, used when the opcode starts with F
    23  
    24  const (
    25  	riscv64REG_G    = 27
    26  	riscv64REG_CTXT = 26
    27  	riscv64REG_LR   = 1
    28  	riscv64REG_SP   = 2
    29  	riscv64REG_GP   = 3
    30  	riscv64REG_TP   = 4
    31  	riscv64REG_TMP  = 31
    32  	riscv64REG_ZERO = 0
    33  )
    34  
    35  func riscv64RegName(r int) string {
    36  	switch {
    37  	case r == riscv64REG_G:
    38  		return "g"
    39  	case r == riscv64REG_SP:
    40  		return "SP"
    41  	case 0 <= r && r <= 31:
    42  		return fmt.Sprintf("X%d", r)
    43  	case 32 <= r && r <= 63:
    44  		return fmt.Sprintf("F%d", r-32)
    45  	default:
    46  		panic(fmt.Sprintf("unknown register %d", r))
    47  	}
    48  }
    49  
    50  func init() {
    51  	var regNamesRISCV64 []string
    52  	var gpMask, fpMask, gpgMask, gpspMask, gpspsbMask, gpspsbgMask, first16Mask regMask
    53  	regNamed := make(map[string]regMask)
    54  
    55  	// Build the list of register names, creating an appropriately indexed
    56  	// regMask for the gp and fp registers as we go.
    57  	//
    58  	// If name is specified, use it rather than the riscv reg number.
    59  	addreg := func(r int, name string) regMask {
    60  		mask := regMask(1) << uint(len(regNamesRISCV64))
    61  		if name == "" {
    62  			name = riscv64RegName(r)
    63  		}
    64  		regNamesRISCV64 = append(regNamesRISCV64, name)
    65  		regNamed[name] = mask
    66  		return mask
    67  	}
    68  
    69  	// General purpose registers.
    70  	for r := 0; r <= 31; r++ {
    71  		if r == riscv64REG_LR {
    72  			// LR is not used by regalloc, so we skip it to leave
    73  			// room for pseudo-register SB.
    74  			continue
    75  		}
    76  
    77  		mask := addreg(r, "")
    78  
    79  		// Add general purpose registers to gpMask.
    80  		switch r {
    81  		// ZERO, GP, TP and TMP are not in any gp mask.
    82  		case riscv64REG_ZERO, riscv64REG_GP, riscv64REG_TP, riscv64REG_TMP:
    83  		case riscv64REG_G:
    84  			gpgMask |= mask
    85  			gpspsbgMask |= mask
    86  		case riscv64REG_SP:
    87  			gpspMask |= mask
    88  			gpspsbMask |= mask
    89  			gpspsbgMask |= mask
    90  		default:
    91  			gpMask |= mask
    92  			gpgMask |= mask
    93  			gpspMask |= mask
    94  			gpspsbMask |= mask
    95  			gpspsbgMask |= mask
    96  			if r >= 5 && r < 5+16 {
    97  				first16Mask |= mask
    98  			}
    99  		}
   100  	}
   101  
   102  	// Floating point registers.
   103  	for r := 32; r <= 63; r++ {
   104  		mask := addreg(r, "")
   105  		fpMask |= mask
   106  	}
   107  
   108  	// Pseudo-register: SB
   109  	mask := addreg(-1, "SB")
   110  	gpspsbMask |= mask
   111  	gpspsbgMask |= mask
   112  
   113  	if len(regNamesRISCV64) > 64 {
   114  		// regMask is only 64 bits.
   115  		panic("Too many RISCV64 registers")
   116  	}
   117  
   118  	regCtxt := regNamed["X26"]
   119  	callerSave := gpMask | fpMask | regNamed["g"]
   120  	r5toR6 := regNamed["X5"] | regNamed["X6"]
   121  	regX5 := regNamed["X5"]
   122  
   123  	var (
   124  		gpstore  = regInfo{inputs: []regMask{gpspsbMask, gpspMask, 0}} // SB in first input so we can load from a global, but not in second to avoid using SB as a temporary register
   125  		gpstore0 = regInfo{inputs: []regMask{gpspsbMask}}
   126  		gp01     = regInfo{outputs: []regMask{gpMask}}
   127  		gp11     = regInfo{inputs: []regMask{gpMask}, outputs: []regMask{gpMask}}
   128  		gp21     = regInfo{inputs: []regMask{gpMask, gpMask}, outputs: []regMask{gpMask}}
   129  		gp22     = regInfo{inputs: []regMask{gpMask, gpMask}, outputs: []regMask{gpMask, gpMask}}
   130  		gpload   = regInfo{inputs: []regMask{gpspsbMask, 0}, outputs: []regMask{gpMask}}
   131  		gp11sb   = regInfo{inputs: []regMask{gpspsbMask}, outputs: []regMask{gpMask}}
   132  		gpxchg   = regInfo{inputs: []regMask{gpspsbgMask, gpgMask}, outputs: []regMask{gpMask}}
   133  		gpcas    = regInfo{inputs: []regMask{gpspsbgMask, gpgMask, gpgMask}, outputs: []regMask{gpMask}}
   134  		gpatomic = regInfo{inputs: []regMask{gpspsbgMask, gpgMask}}
   135  
   136  		fp01    = regInfo{outputs: []regMask{fpMask}}
   137  		fp11    = regInfo{inputs: []regMask{fpMask}, outputs: []regMask{fpMask}}
   138  		fp21    = regInfo{inputs: []regMask{fpMask, fpMask}, outputs: []regMask{fpMask}}
   139  		fp31    = regInfo{inputs: []regMask{fpMask, fpMask, fpMask}, outputs: []regMask{fpMask}}
   140  		gpfp    = regInfo{inputs: []regMask{gpMask}, outputs: []regMask{fpMask}}
   141  		fpgp    = regInfo{inputs: []regMask{fpMask}, outputs: []regMask{gpMask}}
   142  		fpstore = regInfo{inputs: []regMask{gpspsbMask, fpMask, 0}}
   143  		fpload  = regInfo{inputs: []regMask{gpspsbMask, 0}, outputs: []regMask{fpMask}}
   144  		fp2gp   = regInfo{inputs: []regMask{fpMask, fpMask}, outputs: []regMask{gpMask}}
   145  
   146  		call = regInfo{clobbers: callerSave}
   147  		// Avoid using X5 as the source register of calls. Using X5 here triggers
   148  		// RAS pop-then-push behavior which is not correct for function calls.
   149  		// Please refer to section 2.5.1 of the RISC-V ISA
   150  		// (https://docs.riscv.org/reference/isa/unpriv/rv32.html#rashints) for details.
   151  		callClosure = regInfo{inputs: []regMask{gpspMask ^ regX5, regCtxt, 0}, clobbers: callerSave}
   152  		callInter   = regInfo{inputs: []regMask{gpMask ^ regX5}, clobbers: callerSave}
   153  	)
   154  
   155  	RISCV64ops := []opData{
   156  		{name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true}, // arg0 + arg1
   157  		{name: "ADDI", argLength: 1, reg: gp11sb, asm: "ADDI", aux: "Int64"},  // arg0 + auxint
   158  		{name: "ADDIW", argLength: 1, reg: gp11, asm: "ADDIW", aux: "Int64"},  // 32 low bits of arg0 + auxint, sign extended to 64 bits
   159  		{name: "NEG", argLength: 1, reg: gp11, asm: "NEG"},                    // -arg0
   160  		{name: "NEGW", argLength: 1, reg: gp11, asm: "NEGW"},                  // -arg0 of 32 bits, sign extended to 64 bits
   161  		{name: "SUB", argLength: 2, reg: gp21, asm: "SUB"},                    // arg0 - arg1
   162  		{name: "SUBW", argLength: 2, reg: gp21, asm: "SUBW"},                  // 32 low bits of arg 0 - 32 low bits of arg 1, sign extended to 64 bits
   163  
   164  		// M extension. H means high (i.e., it returns the top bits of
   165  		// the result). U means unsigned. W means word (i.e., 32-bit).
   166  		{name: "MUL", argLength: 2, reg: gp21, asm: "MUL", commutative: true, typ: "Int64"}, // arg0 * arg1
   167  		{name: "MULW", argLength: 2, reg: gp21, asm: "MULW", commutative: true, typ: "Int32"},
   168  		{name: "MULH", argLength: 2, reg: gp21, asm: "MULH", commutative: true, typ: "Int64"},
   169  		{name: "MULHU", argLength: 2, reg: gp21, asm: "MULHU", commutative: true, typ: "UInt64"},
   170  		{name: "LoweredMuluhilo", argLength: 2, reg: gp22, resultNotInArgs: true}, // arg0 * arg1, return (hi, lo)
   171  		{name: "LoweredMuluover", argLength: 2, reg: gp22, resultNotInArgs: true}, // arg0 * arg1, return (64 bits of arg0*arg1, overflow)
   172  
   173  		{name: "DIV", argLength: 2, reg: gp21, asm: "DIV", typ: "Int64"}, // arg0 / arg1
   174  		{name: "DIVU", argLength: 2, reg: gp21, asm: "DIVU", typ: "UInt64"},
   175  		{name: "DIVW", argLength: 2, reg: gp21, asm: "DIVW", typ: "Int32"},
   176  		{name: "DIVUW", argLength: 2, reg: gp21, asm: "DIVUW", typ: "UInt32"},
   177  		{name: "REM", argLength: 2, reg: gp21, asm: "REM", typ: "Int64"}, // arg0 % arg1
   178  		{name: "REMU", argLength: 2, reg: gp21, asm: "REMU", typ: "UInt64"},
   179  		{name: "REMW", argLength: 2, reg: gp21, asm: "REMW", typ: "Int32"},
   180  		{name: "REMUW", argLength: 2, reg: gp21, asm: "REMUW", typ: "UInt32"},
   181  
   182  		{name: "MOVaddr", argLength: 1, reg: gp11sb, asm: "MOV", aux: "SymOff", rematerializeable: true, symEffect: "Addr"}, // arg0 + auxint + offset encoded in aux
   183  		// auxint+aux == add auxint and the offset of the symbol in aux (if any) to the effective address
   184  
   185  		{name: "MOVDconst", reg: gp01, asm: "MOV", typ: "UInt64", aux: "Int64", rematerializeable: true},      // auxint
   186  		{name: "FMOVDconst", reg: fp01, asm: "MOVD", typ: "Float64", aux: "Float64", rematerializeable: true}, // auxint
   187  		{name: "FMOVFconst", reg: fp01, asm: "MOVF", typ: "Float32", aux: "Float32", rematerializeable: true}, // auxint
   188  
   189  		// Loads: load <size> bits from arg0+auxint+aux and extend to 64 bits; arg1=mem
   190  		{name: "MOVBload", argLength: 2, reg: gpload, asm: "MOVB", aux: "SymOff", typ: "Int8", faultOnNilArg0: true, symEffect: "Read"},     //  8 bits, sign extend
   191  		{name: "MOVHload", argLength: 2, reg: gpload, asm: "MOVH", aux: "SymOff", typ: "Int16", faultOnNilArg0: true, symEffect: "Read"},    // 16 bits, sign extend
   192  		{name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVW", aux: "SymOff", typ: "Int32", faultOnNilArg0: true, symEffect: "Read"},    // 32 bits, sign extend
   193  		{name: "MOVDload", argLength: 2, reg: gpload, asm: "MOV", aux: "SymOff", typ: "Int64", faultOnNilArg0: true, symEffect: "Read"},     // 64 bits
   194  		{name: "MOVBUload", argLength: 2, reg: gpload, asm: "MOVBU", aux: "SymOff", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read"},  //  8 bits, zero extend
   195  		{name: "MOVHUload", argLength: 2, reg: gpload, asm: "MOVHU", aux: "SymOff", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read"}, // 16 bits, zero extend
   196  		{name: "MOVWUload", argLength: 2, reg: gpload, asm: "MOVWU", aux: "SymOff", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read"}, // 32 bits, zero extend
   197  
   198  		// Stores: store <size> lowest bits in arg1 to arg0+auxint+aux; arg2=mem
   199  		{name: "MOVBstore", argLength: 3, reg: gpstore, asm: "MOVB", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, //  8 bits
   200  		{name: "MOVHstore", argLength: 3, reg: gpstore, asm: "MOVH", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // 16 bits
   201  		{name: "MOVWstore", argLength: 3, reg: gpstore, asm: "MOVW", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // 32 bits
   202  		{name: "MOVDstore", argLength: 3, reg: gpstore, asm: "MOV", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},  // 64 bits
   203  
   204  		// Stores: store <size> of zero in arg0+auxint+aux; arg1=mem
   205  		{name: "MOVBstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, //  8 bits
   206  		{name: "MOVHstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // 16 bits
   207  		{name: "MOVWstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // 32 bits
   208  		{name: "MOVDstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOV", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},  // 64 bits
   209  
   210  		// Conversions
   211  		{name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB"},   // move from arg0, sign-extended from byte
   212  		{name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVH"},   // move from arg0, sign-extended from half
   213  		{name: "MOVWreg", argLength: 1, reg: gp11, asm: "MOVW"},   // move from arg0, sign-extended from word
   214  		{name: "MOVDreg", argLength: 1, reg: gp11, asm: "MOV"},    // move from arg0
   215  		{name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU"}, // move from arg0, unsign-extended from byte
   216  		{name: "MOVHUreg", argLength: 1, reg: gp11, asm: "MOVHU"}, // move from arg0, unsign-extended from half
   217  		{name: "MOVWUreg", argLength: 1, reg: gp11, asm: "MOVWU"}, // move from arg0, unsign-extended from word
   218  
   219  		{name: "MOVDnop", argLength: 1, reg: regInfo{inputs: []regMask{gpMask}, outputs: []regMask{gpMask}}, resultInArg0: true}, // nop, return arg0 in same register
   220  
   221  		// Shift ops
   222  		{name: "SLL", argLength: 2, reg: gp21, asm: "SLL"},                   // arg0 << (aux1 & 63), logical left shift
   223  		{name: "SLLW", argLength: 2, reg: gp21, asm: "SLLW"},                 // arg0 << (aux1 & 31), logical left shift of 32 bit value, sign extended to 64 bits
   224  		{name: "SRA", argLength: 2, reg: gp21, asm: "SRA"},                   // arg0 >> (aux1 & 63), arithmetic right shift
   225  		{name: "SRAW", argLength: 2, reg: gp21, asm: "SRAW"},                 // arg0 >> (aux1 & 31), arithmetic right shift of 32 bit value, sign extended to 64 bits
   226  		{name: "SRL", argLength: 2, reg: gp21, asm: "SRL"},                   // arg0 >> (aux1 & 63), logical right shift
   227  		{name: "SRLW", argLength: 2, reg: gp21, asm: "SRLW"},                 // arg0 >> (aux1 & 31), logical right shift of 32 bit value, sign extended to 64 bits
   228  		{name: "SLLI", argLength: 1, reg: gp11, asm: "SLLI", aux: "Int64"},   // arg0 << auxint, shift amount 0-63, logical left shift
   229  		{name: "SLLIW", argLength: 1, reg: gp11, asm: "SLLIW", aux: "Int64"}, // arg0 << auxint, shift amount 0-31, logical left shift of 32 bit value, sign extended to 64 bits
   230  		{name: "SRAI", argLength: 1, reg: gp11, asm: "SRAI", aux: "Int64"},   // arg0 >> auxint, shift amount 0-63, arithmetic right shift
   231  		{name: "SRAIW", argLength: 1, reg: gp11, asm: "SRAIW", aux: "Int64"}, // arg0 >> auxint, shift amount 0-31, arithmetic right shift of 32 bit value, sign extended to 64 bits
   232  		{name: "SRLI", argLength: 1, reg: gp11, asm: "SRLI", aux: "Int64"},   // arg0 >> auxint, shift amount 0-63, logical right shift
   233  		{name: "SRLIW", argLength: 1, reg: gp11, asm: "SRLIW", aux: "Int64"}, // arg0 >> auxint, shift amount 0-31, logical right shift of 32 bit value, sign extended to 64 bits
   234  
   235  		// Shift and add
   236  		{name: "SH1ADD", argLength: 2, reg: gp21, asm: "SH1ADD"}, // arg0 << 1 + arg1
   237  		{name: "SH2ADD", argLength: 2, reg: gp21, asm: "SH2ADD"}, // arg0 << 2 + arg1
   238  		{name: "SH3ADD", argLength: 2, reg: gp21, asm: "SH3ADD"}, // arg0 << 3 + arg1
   239  
   240  		// Bitwise ops
   241  		{name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true},   // arg0 & arg1
   242  		{name: "ANDN", argLength: 2, reg: gp21, asm: "ANDN"},                    // ^arg0 & arg1
   243  		{name: "ANDI", argLength: 1, reg: gp11, asm: "ANDI", aux: "Int64"},      // arg0 & auxint
   244  		{name: "CLZ", argLength: 1, reg: gp11, asm: "CLZ"},                      // count leading zeros
   245  		{name: "CLZW", argLength: 1, reg: gp11, asm: "CLZW"},                    // count leading zeros of least significant word
   246  		{name: "CPOP", argLength: 1, reg: gp11, asm: "CPOP"},                    // count set bits
   247  		{name: "CPOPW", argLength: 1, reg: gp11, asm: "CPOPW"},                  // count set bits in least significant word
   248  		{name: "CTZ", argLength: 1, reg: gp11, asm: "CTZ"},                      // count trailing zeros
   249  		{name: "CTZW", argLength: 1, reg: gp11, asm: "CTZW"},                    // count trailing zeros of least significant word
   250  		{name: "NOT", argLength: 1, reg: gp11, asm: "NOT"},                      // ^arg0
   251  		{name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true},     // arg0 | arg1
   252  		{name: "ORN", argLength: 2, reg: gp21, asm: "ORN"},                      // ^arg0 | arg1
   253  		{name: "ORI", argLength: 1, reg: gp11, asm: "ORI", aux: "Int64"},        // arg0 | auxint
   254  		{name: "REV8", argLength: 1, reg: gp11, asm: "REV8"},                    // reverse bytes
   255  		{name: "ROL", argLength: 2, reg: gp21, asm: "ROL"},                      // rotate left arg0 by (arg1 & 63)
   256  		{name: "ROLW", argLength: 2, reg: gp21, asm: "ROLW"},                    // rotate left least significant word of arg0 by (arg1 & 31), sign extended
   257  		{name: "ROR", argLength: 2, reg: gp21, asm: "ROR"},                      // rotate right arg0 by (arg1 & 63)
   258  		{name: "RORI", argLength: 1, reg: gp11, asm: "RORI", aux: "Int64"},      // rotate right arg0 by auxint, shift amount 0-63
   259  		{name: "RORIW", argLength: 1, reg: gp11, asm: "RORIW", aux: "Int64"},    // rotate right least significant word of arg0 by auxint, shift amount 0-31, sign extended
   260  		{name: "RORW", argLength: 2, reg: gp21, asm: "RORW"},                    // rotate right least significant word of arg0 by (arg1 & 31), sign extended
   261  		{name: "XNOR", argLength: 2, reg: gp21, asm: "XNOR", commutative: true}, // ^(arg0 ^ arg1)
   262  		{name: "XOR", argLength: 2, reg: gp21, asm: "XOR", commutative: true},   // arg0 ^ arg1
   263  		{name: "XORI", argLength: 1, reg: gp11, asm: "XORI", aux: "Int64"},      // arg0 ^ auxint
   264  
   265  		// Minimum and maximum
   266  		{name: "MIN", argLength: 2, reg: gp21, asm: "MIN", commutative: true},   // min(arg0,arg1), signed
   267  		{name: "MAX", argLength: 2, reg: gp21, asm: "MAX", commutative: true},   // max(arg0,arg1), signed
   268  		{name: "MINU", argLength: 2, reg: gp21, asm: "MINU", commutative: true}, // min(arg0,arg1), unsigned
   269  		{name: "MAXU", argLength: 2, reg: gp21, asm: "MAXU", commutative: true}, // max(arg0,arg1), unsigned
   270  
   271  		// Generate boolean values
   272  		{name: "SEQZ", argLength: 1, reg: gp11, asm: "SEQZ"},                 // arg0 == 0, result is 0 or 1
   273  		{name: "SNEZ", argLength: 1, reg: gp11, asm: "SNEZ"},                 // arg0 != 0, result is 0 or 1
   274  		{name: "SLT", argLength: 2, reg: gp21, asm: "SLT"},                   // arg0 < arg1, result is 0 or 1
   275  		{name: "SLTI", argLength: 1, reg: gp11, asm: "SLTI", aux: "Int64"},   // arg0 < auxint, result is 0 or 1
   276  		{name: "SLTU", argLength: 2, reg: gp21, asm: "SLTU"},                 // arg0 < arg1, unsigned, result is 0 or 1
   277  		{name: "SLTIU", argLength: 1, reg: gp11, asm: "SLTIU", aux: "Int64"}, // arg0 < auxint, unsigned, result is 0 or 1
   278  
   279  		// Round ops to block fused-multiply-add extraction.
   280  		{name: "LoweredRound32F", argLength: 1, reg: fp11, resultInArg0: true},
   281  		{name: "LoweredRound64F", argLength: 1, reg: fp11, resultInArg0: true},
   282  
   283  		// Calls
   284  		{name: "CALLstatic", argLength: -1, reg: call, aux: "CallOff", call: true},                         // call static function aux.(*gc.Sym). last arg=mem, auxint=argsize, returns mem
   285  		{name: "CALLtail", argLength: -1, reg: call, aux: "CallOff", call: true, tailCall: true},           // tail call static function aux.(*gc.Sym). last arg=mem, auxint=argsize, returns mem
   286  		{name: "CALLtailinter", argLength: -1, reg: callInter, aux: "CallOff", call: true, tailCall: true}, // tail call fn by pointer. arg0=codeptr, last arg=mem, auxint=argsize, returns mem
   287  		{name: "CALLclosure", argLength: -1, reg: callClosure, aux: "CallOff", call: true},                 // call function via closure. arg0=codeptr, arg1=closure, last arg=mem, auxint=argsize, returns mem
   288  		{name: "CALLinter", argLength: -1, reg: callInter, aux: "CallOff", call: true},                     // call fn by pointer. arg0=codeptr, last arg=mem, auxint=argsize, returns mem
   289  
   290  		// Generic moves and zeros
   291  
   292  		// general unrolled zeroing
   293  		// arg0 = address of memory to zero
   294  		// arg1 = mem
   295  		// auxint = element size and type alignment
   296  		// returns mem
   297  		//	mov	ZERO, (OFFSET)(Rarg0)
   298  		{
   299  			name:           "LoweredZero",
   300  			aux:            "SymValAndOff",
   301  			typ:            "Mem",
   302  			argLength:      2,
   303  			symEffect:      "Write",
   304  			faultOnNilArg0: true,
   305  			reg: regInfo{
   306  				inputs: []regMask{gpMask},
   307  			},
   308  		},
   309  		// general unaligned zeroing
   310  		// arg0 = address of memory to zero (clobber)
   311  		// arg2 = mem
   312  		// auxint = element size and type alignment
   313  		// returns mem
   314  		{
   315  			name:           "LoweredZeroLoop",
   316  			aux:            "SymValAndOff",
   317  			typ:            "Mem",
   318  			argLength:      2,
   319  			symEffect:      "Write",
   320  			needIntTemp:    true,
   321  			faultOnNilArg0: true,
   322  			reg: regInfo{
   323  				inputs:       []regMask{gpMask},
   324  				clobbersArg0: true,
   325  			},
   326  		},
   327  
   328  		// general unaligned move
   329  		// arg0 = address of dst memory (clobber)
   330  		// arg1 = address of src memory (clobber)
   331  		// arg2 = mem
   332  		// auxint = size and type alignment
   333  		// returns mem
   334  		//	mov	(offset)(Rarg1), TMP
   335  		//	mov	TMP, (offset)(Rarg0)
   336  		{
   337  			name:      "LoweredMove",
   338  			aux:       "SymValAndOff",
   339  			symEffect: "Write",
   340  			argLength: 3,
   341  			reg: regInfo{
   342  				inputs:   []regMask{gpMask &^ regNamed["X5"], gpMask &^ regNamed["X5"]},
   343  				clobbers: regNamed["X5"],
   344  			},
   345  			faultOnNilArg0: true,
   346  			faultOnNilArg1: true,
   347  		},
   348  
   349  		// general unaligned move
   350  		// arg0 = address of dst memory (clobber)
   351  		// arg1 = address of src memory (clobber)
   352  		// arg3 = mem
   353  		// auxint = alignment
   354  		// returns mem
   355  		//	ADD	$sz, X6
   356  		//loop:
   357  		//	mov	(Rarg1), X5
   358  		//	mov	X5, (Rarg0)
   359  		//	...rest 7 mov...
   360  		//	ADD	$sz, Rarg0
   361  		//	ADD	$sz, Rarg1
   362  		//	BNE	X6, Rarg1, loop
   363  		{
   364  			name:      "LoweredMoveLoop",
   365  			aux:       "SymValAndOff",
   366  			argLength: 3,
   367  			symEffect: "Write",
   368  			reg: regInfo{
   369  				inputs:       []regMask{gpMask &^ r5toR6, gpMask &^ r5toR6},
   370  				clobbers:     r5toR6,
   371  				clobbersArg0: true,
   372  				clobbersArg1: true,
   373  			},
   374  			faultOnNilArg0: true,
   375  			faultOnNilArg1: true,
   376  		},
   377  
   378  		// Atomic loads.
   379  		// load from arg0. arg1=mem.
   380  		// returns <value,memory> so they can be properly ordered with other loads.
   381  		{name: "LoweredAtomicLoad8", argLength: 2, reg: gpload, faultOnNilArg0: true},
   382  		{name: "LoweredAtomicLoad32", argLength: 2, reg: gpload, faultOnNilArg0: true},
   383  		{name: "LoweredAtomicLoad64", argLength: 2, reg: gpload, faultOnNilArg0: true},
   384  
   385  		// Atomic stores.
   386  		// store arg1 to *arg0. arg2=mem. returns memory.
   387  		{name: "LoweredAtomicStore8", argLength: 3, reg: gpstore, faultOnNilArg0: true, hasSideEffects: true},
   388  		{name: "LoweredAtomicStore32", argLength: 3, reg: gpstore, faultOnNilArg0: true, hasSideEffects: true},
   389  		{name: "LoweredAtomicStore64", argLength: 3, reg: gpstore, faultOnNilArg0: true, hasSideEffects: true},
   390  
   391  		// Atomic exchange.
   392  		// store arg1 to *arg0. arg2=mem. returns <old content of *arg0, memory>.
   393  		{name: "LoweredAtomicExchange32", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true},
   394  		{name: "LoweredAtomicExchange64", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true},
   395  
   396  		// Atomic add.
   397  		// *arg0 += arg1. arg2=mem. returns <new content of *arg0, memory>.
   398  		{name: "LoweredAtomicAdd32", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
   399  		{name: "LoweredAtomicAdd64", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
   400  
   401  		// Atomic compare and swap.
   402  		// arg0 = pointer, arg1 = old value, arg2 = new value, arg3 = memory.
   403  		// if *arg0 == arg1 {
   404  		//   *arg0 = arg2
   405  		//   return (true, memory)
   406  		// } else {
   407  		//   return (false, memory)
   408  		// }
   409  		// MOV  $0, Rout
   410  		// LR	(Rarg0), Rtmp
   411  		// BNE	Rtmp, Rarg1, 3(PC)
   412  		// SC	Rarg2, (Rarg0), Rtmp
   413  		// BNE	Rtmp, ZERO, -3(PC)
   414  		// MOV  $1, Rout
   415  		{name: "LoweredAtomicCas32", argLength: 4, reg: gpcas, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
   416  		{name: "LoweredAtomicCas64", argLength: 4, reg: gpcas, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
   417  
   418  		// Atomic 32 bit AND/OR.
   419  		// *arg0 &= (|=) arg1. arg2=mem. returns nil.
   420  		{name: "LoweredAtomicAnd32", argLength: 3, reg: gpatomic, asm: "AMOANDW", faultOnNilArg0: true, hasSideEffects: true},
   421  		{name: "LoweredAtomicOr32", argLength: 3, reg: gpatomic, asm: "AMOORW", faultOnNilArg0: true, hasSideEffects: true},
   422  
   423  		// Lowering pass-throughs
   424  		{name: "LoweredNilCheck", argLength: 2, faultOnNilArg0: true, nilCheck: true, reg: regInfo{inputs: []regMask{gpspMask}}}, // arg0=ptr,arg1=mem, returns void.  Faults if ptr is nil.
   425  		{name: "LoweredGetClosurePtr", reg: regInfo{outputs: []regMask{regCtxt}}},                                                // scheduler ensures only at beginning of entry block
   426  
   427  		// LoweredGetCallerSP returns the SP of the caller of the current function. arg0=mem.
   428  		{name: "LoweredGetCallerSP", argLength: 1, reg: gp01, rematerializeable: true},
   429  
   430  		// LoweredGetCallerPC evaluates to the PC to which its "caller" will return.
   431  		// I.e., if f calls g "calls" sys.GetCallerPC,
   432  		// the result should be the PC within f that g will return to.
   433  		// See runtime/stubs.go for a more detailed discussion.
   434  		{name: "LoweredGetCallerPC", reg: gp01, rematerializeable: true},
   435  
   436  		// LoweredWB invokes runtime.gcWriteBarrier. arg0=mem, auxint=# of buffer entries needed
   437  		// It saves all GP registers if necessary,
   438  		// but clobbers RA (LR) because it's a call
   439  		// and T6 (REG_TMP).
   440  		// Returns a pointer to a write barrier buffer in X24.
   441  		{name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: (callerSave &^ (gpMask | regNamed["g"])) | regNamed["X1"], outputs: []regMask{regNamed["X24"]}}, clobberFlags: true, aux: "Int64"},
   442  
   443  		// Do data barrier. arg0=memorys
   444  		{name: "LoweredPubBarrier", argLength: 1, asm: "FENCE", hasSideEffects: true},
   445  
   446  		// LoweredPanicBoundsRR takes x and y, two values that caused a bounds check to fail.
   447  		// the RC and CR versions are used when one of the arguments is a constant. CC is used
   448  		// when both are constant (normally both 0, as prove derives the fact that a [0] bounds
   449  		// failure means the length must have also been 0).
   450  		// AuxInt contains a report code (see PanicBounds in genericOps.go).
   451  		{name: "LoweredPanicBoundsRR", argLength: 3, aux: "Int64", reg: regInfo{inputs: []regMask{first16Mask, first16Mask}}, typ: "Mem", call: true}, // arg0=x, arg1=y, arg2=mem, returns memory.
   452  		{name: "LoweredPanicBoundsRC", argLength: 2, aux: "PanicBoundsC", reg: regInfo{inputs: []regMask{first16Mask}}, typ: "Mem", call: true},       // arg0=x, arg1=mem, returns memory.
   453  		{name: "LoweredPanicBoundsCR", argLength: 2, aux: "PanicBoundsC", reg: regInfo{inputs: []regMask{first16Mask}}, typ: "Mem", call: true},       // arg0=y, arg1=mem, returns memory.
   454  		{name: "LoweredPanicBoundsCC", argLength: 1, aux: "PanicBoundsCC", reg: regInfo{}, typ: "Mem", call: true},                                    // arg0=mem, returns memory.
   455  
   456  		// F extension.
   457  		{name: "FADDS", argLength: 2, reg: fp21, asm: "FADDS", commutative: true, typ: "Float32"},                                           // arg0 + arg1
   458  		{name: "FSUBS", argLength: 2, reg: fp21, asm: "FSUBS", commutative: false, typ: "Float32"},                                          // arg0 - arg1
   459  		{name: "FMULS", argLength: 2, reg: fp21, asm: "FMULS", commutative: true, typ: "Float32"},                                           // arg0 * arg1
   460  		{name: "FDIVS", argLength: 2, reg: fp21, asm: "FDIVS", commutative: false, typ: "Float32"},                                          // arg0 / arg1
   461  		{name: "FMADDS", argLength: 3, reg: fp31, asm: "FMADDS", commutative: true, typ: "Float32"},                                         // (arg0 * arg1) + arg2
   462  		{name: "FMSUBS", argLength: 3, reg: fp31, asm: "FMSUBS", commutative: true, typ: "Float32"},                                         // (arg0 * arg1) - arg2
   463  		{name: "FNMADDS", argLength: 3, reg: fp31, asm: "FNMADDS", commutative: true, typ: "Float32"},                                       // -(arg0 * arg1) + arg2
   464  		{name: "FNMSUBS", argLength: 3, reg: fp31, asm: "FNMSUBS", commutative: true, typ: "Float32"},                                       // -(arg0 * arg1) - arg2
   465  		{name: "FSQRTS", argLength: 1, reg: fp11, asm: "FSQRTS", typ: "Float32"},                                                            // sqrt(arg0)
   466  		{name: "FABSS", argLength: 1, reg: fp11, asm: "FABSS", typ: "Float32"},                                                              // abs(arg0)
   467  		{name: "FNEGS", argLength: 1, reg: fp11, asm: "FNEGS", typ: "Float32"},                                                              // -arg0
   468  		{name: "FMVSX", argLength: 1, reg: gpfp, asm: "FMVSX", typ: "Float32"},                                                              // reinterpret arg0 as float32
   469  		{name: "FMVXS", argLength: 1, reg: fpgp, asm: "FMVXS", typ: "Int32"},                                                                // reinterpret arg0 as int32, sign extended to 64 bits
   470  		{name: "FCVTSW", argLength: 1, reg: gpfp, asm: "FCVTSW", typ: "Float32"},                                                            // float32(low 32 bits of arg0)
   471  		{name: "FCVTSL", argLength: 1, reg: gpfp, asm: "FCVTSL", typ: "Float32"},                                                            // float32(arg0)
   472  		{name: "FCVTWS", argLength: 1, reg: fpgp, asm: "FCVTWS", typ: "Int32"},                                                              // int32(arg0)
   473  		{name: "FCVTLS", argLength: 1, reg: fpgp, asm: "FCVTLS", typ: "Int64"},                                                              // int64(arg0)
   474  		{name: "FMOVWload", argLength: 2, reg: fpload, asm: "MOVF", aux: "SymOff", typ: "Float32", faultOnNilArg0: true, symEffect: "Read"}, // load float32 from arg0+auxint+aux
   475  		{name: "FMOVWstore", argLength: 3, reg: fpstore, asm: "MOVF", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},  // store float32 to arg0+auxint+aux
   476  		{name: "FEQS", argLength: 2, reg: fp2gp, asm: "FEQS", commutative: true},                                                            // arg0 == arg1
   477  		{name: "FNES", argLength: 2, reg: fp2gp, asm: "FNES", commutative: true},                                                            // arg0 != arg1
   478  		{name: "FLTS", argLength: 2, reg: fp2gp, asm: "FLTS"},                                                                               // arg0 < arg1
   479  		{name: "FLES", argLength: 2, reg: fp2gp, asm: "FLES"},                                                                               // arg0 <= arg1
   480  		{name: "LoweredFMAXS", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMAXS", commutative: true, typ: "Float32"},             // max(arg0, arg1)
   481  		{name: "LoweredFMINS", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMINS", commutative: true, typ: "Float32"},             // min(arg0, arg1)
   482  
   483  		// D extension.
   484  		{name: "FADDD", argLength: 2, reg: fp21, asm: "FADDD", commutative: true, typ: "Float64"},                                           // arg0 + arg1
   485  		{name: "FSUBD", argLength: 2, reg: fp21, asm: "FSUBD", commutative: false, typ: "Float64"},                                          // arg0 - arg1
   486  		{name: "FMULD", argLength: 2, reg: fp21, asm: "FMULD", commutative: true, typ: "Float64"},                                           // arg0 * arg1
   487  		{name: "FDIVD", argLength: 2, reg: fp21, asm: "FDIVD", commutative: false, typ: "Float64"},                                          // arg0 / arg1
   488  		{name: "FMADDD", argLength: 3, reg: fp31, asm: "FMADDD", commutative: true, typ: "Float64"},                                         // (arg0 * arg1) + arg2
   489  		{name: "FMSUBD", argLength: 3, reg: fp31, asm: "FMSUBD", commutative: true, typ: "Float64"},                                         // (arg0 * arg1) - arg2
   490  		{name: "FNMADDD", argLength: 3, reg: fp31, asm: "FNMADDD", commutative: true, typ: "Float64"},                                       // -(arg0 * arg1) + arg2
   491  		{name: "FNMSUBD", argLength: 3, reg: fp31, asm: "FNMSUBD", commutative: true, typ: "Float64"},                                       // -(arg0 * arg1) - arg2
   492  		{name: "FSQRTD", argLength: 1, reg: fp11, asm: "FSQRTD", typ: "Float64"},                                                            // sqrt(arg0)
   493  		{name: "FNEGD", argLength: 1, reg: fp11, asm: "FNEGD", typ: "Float64"},                                                              // -arg0
   494  		{name: "FABSD", argLength: 1, reg: fp11, asm: "FABSD", typ: "Float64"},                                                              // abs(arg0)
   495  		{name: "FSGNJD", argLength: 2, reg: fp21, asm: "FSGNJD", typ: "Float64"},                                                            // copy sign of arg1 to arg0
   496  		{name: "FMVDX", argLength: 1, reg: gpfp, asm: "FMVDX", typ: "Float64"},                                                              // reinterpret arg0 as float64
   497  		{name: "FMVXD", argLength: 1, reg: fpgp, asm: "FMVXD", typ: "Int64"},                                                                // reinterpret arg0 as int64
   498  		{name: "FCVTDW", argLength: 1, reg: gpfp, asm: "FCVTDW", typ: "Float64"},                                                            // float64(low 32 bits of arg0)
   499  		{name: "FCVTDL", argLength: 1, reg: gpfp, asm: "FCVTDL", typ: "Float64"},                                                            // float64(arg0)
   500  		{name: "FCVTWD", argLength: 1, reg: fpgp, asm: "FCVTWD", typ: "Int32"},                                                              // int32(arg0)
   501  		{name: "FCVTLD", argLength: 1, reg: fpgp, asm: "FCVTLD", typ: "Int64"},                                                              // int64(arg0)
   502  		{name: "FCVTDS", argLength: 1, reg: fp11, asm: "FCVTDS", typ: "Float64"},                                                            // float64(arg0)
   503  		{name: "FCVTSD", argLength: 1, reg: fp11, asm: "FCVTSD", typ: "Float32"},                                                            // float32(arg0)
   504  		{name: "FMOVDload", argLength: 2, reg: fpload, asm: "MOVD", aux: "SymOff", typ: "Float64", faultOnNilArg0: true, symEffect: "Read"}, // load float64 from arg0+auxint+aux
   505  		{name: "FMOVDstore", argLength: 3, reg: fpstore, asm: "MOVD", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},  // store float6 to arg0+auxint+aux
   506  		{name: "FEQD", argLength: 2, reg: fp2gp, asm: "FEQD", commutative: true},                                                            // arg0 == arg1
   507  		{name: "FNED", argLength: 2, reg: fp2gp, asm: "FNED", commutative: true},                                                            // arg0 != arg1
   508  		{name: "FLTD", argLength: 2, reg: fp2gp, asm: "FLTD"},                                                                               // arg0 < arg1
   509  		{name: "FLED", argLength: 2, reg: fp2gp, asm: "FLED"},                                                                               // arg0 <= arg1
   510  		{name: "LoweredFMIND", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMIND", commutative: true, typ: "Float64"},             // min(arg0, arg1)
   511  		{name: "LoweredFMAXD", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMAXD", commutative: true, typ: "Float64"},             // max(arg0, arg1)
   512  
   513  		// Floating point classify (in the F and D extensions).
   514  		//
   515  		// The FCLASS instructions will always set exactly one bit in the output
   516  		// register, all other bits will be cleared.
   517  		//
   518  		//   Bit | Class
   519  		//   ====+=============================
   520  		//     0 | -∞
   521  		//     1 | a negative normal number
   522  		//     2 | a negative subnormal number
   523  		//     3 | -0
   524  		//     4 | +0
   525  		//     5 | a positive subnormal number
   526  		//     6 | a positive normal number
   527  		//     7 | +∞
   528  		//     8 | qNaN
   529  		//     9 | sNaN
   530  		//   ====+=============================
   531  		{name: "FCLASSS", argLength: 1, reg: fpgp, asm: "FCLASSS", typ: "Int64"}, // classify float32
   532  		{name: "FCLASSD", argLength: 1, reg: fpgp, asm: "FCLASSD", typ: "Int64"}, // classify float64
   533  
   534  		// RISC-V Integer Conditional (Zicond) operations extension
   535  		{name: "CZEROEQZ", argLength: 2, reg: gp21, asm: "CZEROEQZ"}, // arg1 == 0 result is 0, else arg0
   536  		{name: "CZERONEZ", argLength: 2, reg: gp21, asm: "CZERONEZ"}, // arg1 != 0 result is 0, else arg0
   537  	}
   538  
   539  	RISCV64blocks := []blockData{
   540  		{name: "BEQ", controls: 2},
   541  		{name: "BNE", controls: 2},
   542  		{name: "BLT", controls: 2},
   543  		{name: "BGE", controls: 2},
   544  		{name: "BLTU", controls: 2},
   545  		{name: "BGEU", controls: 2},
   546  
   547  		{name: "BEQZ", controls: 1},
   548  		{name: "BNEZ", controls: 1},
   549  		{name: "BLEZ", controls: 1},
   550  		{name: "BGEZ", controls: 1},
   551  		{name: "BLTZ", controls: 1},
   552  		{name: "BGTZ", controls: 1},
   553  	}
   554  
   555  	archs = append(archs, arch{
   556  		name:            "RISCV64",
   557  		pkg:             "cmd/internal/obj/riscv",
   558  		genfile:         "../../riscv64/ssa.go",
   559  		ops:             RISCV64ops,
   560  		blocks:          RISCV64blocks,
   561  		regnames:        regNamesRISCV64,
   562  		gpregmask:       gpMask,
   563  		fpregmask:       fpMask,
   564  		framepointerreg: -1, // not used
   565  		// Integer parameters passed in register X10-X17, X8-X9, X18-X23
   566  		ParamIntRegNames: "X10 X11 X12 X13 X14 X15 X16 X17 X8 X9 X18 X19 X20 X21 X22 X23",
   567  		// Float parameters passed in register F10-F17, F8-F9, F18-F23
   568  		ParamFloatRegNames: "F10 F11 F12 F13 F14 F15 F16 F17 F8 F9 F18 F19 F20 F21 F22 F23",
   569  	})
   570  }
   571
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